{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:28Z","timestamp":1750307908945,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":8,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,3,11]],"date-time":"2007-03-11T00:00:00Z","timestamp":1173571200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,3,11]]},"DOI":"10.1145\/1228784.1228898","type":"proceedings-article","created":{"date-parts":[[2007,4,5]],"date-time":"2007-04-05T19:41:00Z","timestamp":1175802060000},"page":"481-484","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath"],"prefix":"10.1145","author":[{"given":"Koji","family":"Ohashi","sequence":"first","affiliation":[{"name":"Japan Advanced Institute of Science and Technology, Ishikawa, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mineo","family":"Kaneko","sequence":"additional","affiliation":[{"name":"Japan Advanced Institute of Science and Technology, Ishikawa, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,3,11]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"8","article-title":"Synthesis of Two-Phase Quasi-Delay-Insensitive Circuits from Dependence Graphs","volume":"77","author":"Kagotani H.","year":"1994","journal-title":"IEICE Trans. Information and Systems"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.282445"},{"key":"e_1_3_2_1_3_1","first-page":"2","article-title":"An Architecture of FPGA for Dual-Rail Two-Phase Asynchronous Circuits","volume":"86","author":"Saito S.","year":"2003","journal-title":"IEICE Trans. Information and Systems"},{"key":"e_1_3_2_1_4_1","first-page":"354","volume-title":"Proc. International Conf. Computer Design","author":"Bachman B. M.","year":"1999"},{"key":"e_1_3_2_1_5_1","first-page":"115","volume-title":"VLD2004-80","volume":"2004","author":"Saito H.","year":"2004"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2004.86"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378480"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.100"}],"event":{"name":"GLSVLSI07: Great Lakes Symposium on VLSI 2007","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Stresa-Lago Maggiore Italy","acronym":"GLSVLSI07"},"container-title":["Proceedings of the 17th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1228784.1228898","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1228784.1228898","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:47:47Z","timestamp":1750258067000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1228784.1228898"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3,11]]},"references-count":8,"alternative-id":["10.1145\/1228784.1228898","10.1145\/1228784"],"URL":"https:\/\/doi.org\/10.1145\/1228784.1228898","relation":{},"subject":[],"published":{"date-parts":[[2007,3,11]]},"assertion":[{"value":"2007-03-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}