{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:17Z","timestamp":1750307897230,"version":"3.41.0"},"reference-count":31,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2007,4,1]],"date-time":"2007-04-01T00:00:00Z","timestamp":1175385600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2007,4]]},"abstract":"<jats:p>Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to block transitions propagating from the outputs of scan cells through combinational logic. In order to accomplish this, some researchers have proposed setting primary inputs to appropriate values or adding extra gates at the outputs of scan cells. In this article, we point out the limitations of such<jats:italic>full gating<\/jats:italic>techniques in terms of area overhead and performance degradation. We propose an alternate solution where a partial set of scan cells is gated. A subset of scan cells is selected to give maximum reduction in test power within a given area constraint. An alternate formulation of the problem is to treat maximum permitted test power as a constraint and achieve a test power that is within this limit using the fewest number of gated scan cells, thereby leading to the least impact in area overhead. Our problem formulation also comprehends performance constraints and prevents the inclusion of gating points on critical paths. The area overhead is predictable and closely corresponds to the average power reduction.<\/jats:p>","DOI":"10.1145\/1230800.1230809","type":"journal-article","created":{"date-parts":[[2007,6,6]],"date-time":"2007-06-06T14:37:11Z","timestamp":1181140631000},"page":"17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["A critical-path-aware partial gating approach for test power reduction"],"prefix":"10.1145","volume":"12","author":[{"given":"Mohammed","family":"Elshoukry","sequence":"first","affiliation":[{"name":"University of Maryland, Baltimore County, MD"}]},{"given":"Mohammad","family":"Tehranipoor","sequence":"additional","affiliation":[{"name":"University of Connecticut, Storrs, CT"}]},{"given":"C. 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A novel low-power scan design technique using supply gating . In Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors (ICCD). 60--65 . Bhunia, S., Mahmoodi, H., Mukhopadhyay, S., Ghosh, D., and Roy, K. 2004. A novel low-power scan design technique using supply gating. In Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors (ICCD). 60--65."},{"key":"e_1_2_1_3_1","unstructured":"Bushnell M. L. and Agrawal V. D. 2000. Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits. Kluwer Academic Boston MA. Bushnell M. L. and Agrawal V. D. 2000. Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits. 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