{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:54:48Z","timestamp":1750308888328,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,3,17]],"date-time":"2007-03-17T00:00:00Z","timestamp":1174089600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,3,17]]},"DOI":"10.1145\/1231956.1231977","type":"proceedings-article","created":{"date-parts":[[2007,4,5]],"date-time":"2007-04-05T19:41:00Z","timestamp":1175802060000},"page":"103-110","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Exploiting on-chip data behavior for delay minimization"],"prefix":"10.1145","author":[{"given":"Nallamothu","family":"Satyanarayana","sequence":"first","affiliation":[{"name":"Adams Engineering College, Paloncha, Khammam, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Madhu","family":"Mutyam","sequence":"additional","affiliation":[{"name":"International Institute of Information Technology: Hyderabad, Hyderabad, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A Vinaya","family":"Babu","sequence":"additional","affiliation":[{"name":"Jawaharlal Nehru Technological University: Hyderabad, Hyderabad, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,3,17]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Predictive technology model.http:\/\/eas.asuedu\/~ptm  Predictive technology model.http:\/\/eas.asuedu\/~ptm"},{"volume-title":"CPU2000 Benchmark.http:\/\/www.spec.org","author":"SPEC","key":"e_1_3_2_1_2_1","unstructured":"SPEC CPU2000 Benchmark.http:\/\/www.spec.org SPEC CPU2000 Benchmark.http:\/\/www.spec.org"},{"key":"e_1_3_2_1_3_1","unstructured":"Simplescalar Tool-set. http:\/\/www.simplescalar.com  Simplescalar Tool-set. http:\/\/www.simplescalar.com"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/851035.856363"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920583"},{"key":"e_1_3_2_1_6_1","first-page":"778","article-title":"Exploiting crosstalk to speed up on-chip buses","author":"Duan C.","year":"2004","unstructured":"C. Duan and S. P. Khatri . \" Exploiting crosstalk to speed up on-chip buses \". In DATE 2004 , pp. 778 -- 783 . C. Duan and S. P. Khatri. \"Exploiting crosstalk to speed up on-chip buses\". In DATE 2004, pp. 778--783.","journal-title":"DATE"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/572719.876341"},{"key":"e_1_3_2_1_8_1","volume-title":"POTMOS","author":"Guardiani C.","year":"1998","unstructured":"C. Guardiani , C. Forzan , B. Franzini , and D. Pandini . \" Modeling the effect of wire resistance in deep submicron coupled interconnects for accurate crosstalk based net sorting \". In POTMOS 1998 . C. Guardiani, C. Forzan, B. Franzini, and D. Pandini. \"Modeling the effect of wire resistance in deep submicron coupled interconnects for accurate crosstalk based net sorting\". In POTMOS 1998."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/876877.879182"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/505306.505331"},{"key":"e_1_3_2_1_11_1","first-page":"585","volume-title":"POTMOS 2004","author":"Khan Z.","unstructured":"Z. Khan , T. Arslan , and A. T. Erdogan . \" A dual low power and crosstalk immune encoding scheme for system-on-chip buses \". In POTMOS 2004 ,pp. 585 -- 592 . Z. Khan, T. Arslan, and A. T. Erdogan. \"A dual low power and crosstalk immune encoding scheme for system-on-chip buses\". In POTMOS 2004 ,pp. 585--592."},{"key":"e_1_3_2_1_12_1","first-page":"102","article-title":"A crosstalk aware interconnect with variable cycle transmission","author":"Li L.","year":"2004","unstructured":"L. Li , N. Vijaykrishnan , M. Kandemir , and M. J. Irwin . \" A crosstalk aware interconnect with variable cycle transmission \". In DATE 2004 , pp. 102 -- 107 . L. Li, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. \"A crosstalk aware interconnect with variable cycle transmission\". In DATE 2004, pp. 102--107.","journal-title":"DATE"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/603095.603162"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.33"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127938"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/639929.639933"},{"key":"e_1_3_2_1_17_1","first-page":"322","volume-title":"ICCAD","author":"Sotiriadis P.","year":"2000","unstructured":"P. Sotiriadis and A. Chandrakasan . \" Bus energy minimization by transition pattern coding (TPC)in deep sub-micron technologies \". In ICCAD 2000 , pp. 322 -- 327 . P. Sotiriadis and A. Chandrakasan. \"Bus energy minimization by transition pattern coding (TPC)in deep sub-micron technologies\". In ICCAD 2000, pp. 322--327."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370294"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/1032648.1033331"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.848816"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929648"},{"key":"e_1_3_2_1_22_1","volume-title":"DATE","author":"Tiehan L.","year":"2003","unstructured":"L. Tiehan , J. Henkel , H. Lekatsas , and W. Wolf . \" Enhancing signal integrity through a low overhead encoding scheme on address buses \". In DATE 2003 . L. Tiehan, J. Henkel, H. Lekatsas, and W. Wolf. \"Enhancing signal integrity through a low overhead encoding scheme on address buses\". In DATE 2003."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/603095.603107"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309984"}],"event":{"name":"SLIP07: International Workshop on System Level Interconnect Prediction","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Austin Texas USA","acronym":"SLIP07"},"container-title":["Proceedings of the 2007 international workshop on System level interconnect prediction"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1231956.1231977","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1231956.1231977","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:25:35Z","timestamp":1750281935000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1231956.1231977"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3,17]]},"references-count":24,"alternative-id":["10.1145\/1231956.1231977","10.1145\/1231956"],"URL":"https:\/\/doi.org\/10.1145\/1231956.1231977","relation":{},"subject":[],"published":{"date-parts":[[2007,3,17]]},"assertion":[{"value":"2007-03-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}