{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,16]],"date-time":"2026-03-16T10:11:08Z","timestamp":1773655868946,"version":"3.50.1"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2007,3,1]],"date-time":"2007-03-01T00:00:00Z","timestamp":1172707200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,3]]},"abstract":"<jats:p>Recently, a single chip multiprocessor (CMP) is becoming an attractive architecture for improving throughput of program execution. In CMPs, multiple processor cores share several hardware resources such as cache memory and memory bus. Therefore, the resource contention significantly degrades performance of each thread and also loses fairness between threads.<\/jats:p>\n          <jats:p>In this paper, we propose a Dynamic Frequency and Voltage Scaling (DVFS) algorithm for improving total instruction throughput, fairness, and energy efficiency of CMPs. The proposed technique periodically observes the utilization ratio of shared resources and controls the frequency and the voltage of each processor core individually to balance the ratio between threads. We evaluate our technique and the evaluation results show that fairness between threads are greatly improved by the technique. Moreover, the total instruction throughput increases in many cases while reducing energy consumption.<\/jats:p>","DOI":"10.1145\/1241601.1241609","type":"journal-article","created":{"date-parts":[[2007,6,6]],"date-time":"2007-06-06T14:37:16Z","timestamp":1181140636000},"page":"31-38","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":24,"title":["Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS"],"prefix":"10.1145","volume":"35","author":[{"given":"Masaaki","family":"Kondo","sequence":"first","affiliation":[{"name":"The University of Tokyo, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroshi","family":"Sasaki","sequence":"additional","affiliation":[{"name":"The University of Tokyo, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroshi","family":"Nakamura","sequence":"additional","affiliation":[{"name":"The University of Tokyo, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.27"},{"key":"e_1_2_1_5_1","first-page":"132","volume-title":"2005 ISSCC","author":"Fujiyoshi T.","year":"2005","unstructured":"T. Fujiyoshi and et al. Intel pentium m processor datasheet . In 2005 ISSCC , pages 132 -- 133 , Feb. 2005 . T. Fujiyoshi and et al. Intel pentium m processor datasheet. In 2005 ISSCC, pages 132--133, Feb. 2005."},{"key":"e_1_2_1_6_1","volume-title":"June","year":"2003","unstructured":"Intel. Intel Pentium M Processor Datasheet ., June 2003 . Intel. Intel Pentium M Processor Datasheet., June 2003."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545233"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1025127.1026001"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.25"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.211"},{"key":"e_1_2_1_11_1","first-page":"164","volume-title":"ISPASS2001","author":"Luo K.","year":"2001","unstructured":"K. Luo , J. Gummaraju , and M. Franklin . Balancing throughput and fairness in smt processors . In ISPASS2001 , pages 164 -- 171 , Nov. 2001 . K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in smt processors. In ISPASS2001, pages 164--171, Nov. 2001."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859621"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.74"},{"key":"e_1_2_1_14_1","first-page":"296","volume-title":"2005 ISSCC","author":"Nose K.","year":"2005","unstructured":"K. Nose and et al. Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multicore socs . In 2005 ISSCC , pages 296 -- 297 , Feb. 2005 . K. Nose and et al. Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multicore socs. 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