{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:37Z","timestamp":1750307917825,"version":"3.41.0"},"reference-count":31,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2007,3,1]],"date-time":"2007-03-01T00:00:00Z","timestamp":1172707200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,3]]},"abstract":"<jats:p>Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to provide increased concurrency, rather than increased clock speed, for both large-scale as well as embedded systems. Traditionally lock-based synchronization is provided to support concurrency; however, managing locks can be very difficult and error prone. In addition, the performance and power cost of lock-based synchronization can be high. Transactional memories have been extensively investigated as an alternative to lock-based synchronization in general-purpose systems. It has been shown that transactional memory has advantages over locks in terms of ease of programming, performance and energy consumption. However, their applicability to embedded multi-core platforms has not been explored yet. In this paper, we demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCore. Using cycle accurate power and performance models for the transactional memory hardware, we evaluate our architectural framework over a set of different system and application settings, and show that transactional memory is a promising solution, even for resource-constrained embedded multiprocessors.<\/jats:p>","DOI":"10.1145\/1241601.1241611","type":"journal-article","created":{"date-parts":[[2007,6,6]],"date-time":"2007-06-06T14:37:16Z","timestamp":1181140636000},"page":"47-54","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["A hardware\/software framework for supporting transactional memory in a MPSoC environment"],"prefix":"10.1145","volume":"35","author":[{"given":"Cesare","family":"Ferri","sequence":"first","affiliation":[{"name":"Brown University, Providence, RI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tali","family":"Moreshet","sequence":"additional","affiliation":[{"name":"Swarthmore College, Swarthmore, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R. Iris","family":"Bahar","sequence":"additional","affiliation":[{"name":"Brown University, Providence, RI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"University of Bologna, Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maurice","family":"Herlihy","sequence":"additional","affiliation":[{"name":"Brown University, Providence, RI"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,3]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ARM Ltd. The advanced microcontroller bus architecture (AMBA) homepage. www.arm.com\/products\/solutions\/AMBAHomePage.html.  ARM Ltd. The advanced microcontroller bus architecture (AMBA) homepage. www.arm.com\/products\/solutions\/AMBAHomePage.html."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1131481.1131797"},{"key":"e_1_2_1_5_1","unstructured":"MPCore multiprocessor family. www.arm.com.  MPCore multiprocessor family. www.arm.com."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/774789.774805"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_2_1_8_1","volume-title":"Intel","author":"Borkar S.","year":"2005","unstructured":"S. Borkar and et al. Platform 2015: Intel processor and platform evolution for the next decade. Technical report , Intel , 2005 . White Paper. S. Borkar and et al. Platform 2015: Intel processor and platform evolution for the next decade. Technical report, Intel, 2005. White Paper."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469191"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/949305.949340"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065944.1065952"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/872035.872048"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/968879.969124"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605400"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/259380.259442"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"e_1_2_1_19_1","volume-title":"Locks. In Workshop on Memory Performance Issues","author":"Moreshet T.","year":"2006","unstructured":"T. Moreshet , R. I. Bahar , and M. Herlihy . Energy-Aware Microprocessor Synchronization: Transactional Memory vs . Locks. In Workshop on Memory Performance Issues , February 2006 . in conjunction with HPCA. T. Moreshet, R. I. Bahar, and M. Herlihy. Energy-Aware Microprocessor Synchronization: Transactional Memory vs. Locks. In Workshop on Memory Performance Issues, February 2006. in conjunction with HPCA."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598129"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605417"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878259"},{"key":"e_1_2_1_23_1","unstructured":"Philips nexperia platform. www.semiconductors.philips.com.  Philips nexperia platform. www.semiconductors.philips.com."},{"key":"e_1_2_1_24_1","unstructured":"PC205 platform. www.picochip.com.  PC205 platform. www.picochip.com."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605399"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.54"},{"key":"e_1_2_1_27_1","volume-title":"Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections. In International Parallel and Distributed Processing Symposium","author":"Rundberg P.","year":"2003","unstructured":"P. Rundberg and P. Stenstr\u00f6m . Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections. In International Parallel and Distributed Processing Symposium , April 2003 . P. Rundberg and P. Stenstr\u00f6m. Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections. In International Parallel and Distributed Processing Symposium, April 2003."},{"key":"e_1_2_1_28_1","volume-title":"Special Issue(10):99--116","author":"Shavit N.","year":"1997","unstructured":"N. Shavit and D. Touitou . Software transactional memory. Distributed Computing , Special Issue(10):99--116 , 1997 . N. Shavit and D. Touitou. Software transactional memory. Distributed Computing, Special Issue(10):99--116, 1997."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545229"},{"key":"e_1_2_1_30_1","unstructured":"Nomadik platform. www.st.com.  Nomadik platform. www.st.com."},{"key":"e_1_2_1_31_1","unstructured":"STMicroelectronics. www.stm.com.  STMicroelectronics. www.stm.com."},{"key":"e_1_2_1_32_1","unstructured":"OMAP5910 platform. www.ti.com.  OMAP5910 platform. www.ti.com."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1241601.1241611","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1241601.1241611","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:51:26Z","timestamp":1750258286000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1241601.1241611"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3]]},"references-count":31,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2007,3]]}},"alternative-id":["10.1145\/1241601.1241611"],"URL":"https:\/\/doi.org\/10.1145\/1241601.1241611","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2007,3]]},"assertion":[{"value":"2007-03-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}