{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:37Z","timestamp":1750307917117,"version":"3.41.0"},"reference-count":11,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2007,3,1]],"date-time":"2007-03-01T00:00:00Z","timestamp":1172707200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,3]]},"abstract":"<jats:p>SPEC CPU2006 is a compute-intensive industry standard benchmark suite published in August 2006. This paper characterizes the memory access behavior of SPEC CPU2006 running on IBM POWER5+ microprocessors. We measure the maximum and average memory usage of the benchmarks to validate SPEC's memory requirement criteria. This paper also analyzes how different page sizes affect the performance of the benchmarks. The experiment reveals that 64 KB and 16 MB pages improve the performance up to 46.9% and 50.9%, respectively.<\/jats:p>","DOI":"10.1145\/1241601.1241620","type":"journal-article","created":{"date-parts":[[2007,6,6]],"date-time":"2007-06-06T14:37:16Z","timestamp":1181140636000},"page":"97-101","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["SPEC CPU2006 sensitivity to memory page sizes"],"prefix":"10.1145","volume":"35","author":[{"given":"Wendy","family":"Korn","sequence":"first","affiliation":[{"name":"IBM"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Moon S.","family":"Chang","sequence":"additional","affiliation":[{"name":"IBM"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_2_1_3_1","unstructured":"Hepkin D. Guide to Multiple Page Size Support on AIX 5L Version 5.3. IBM whitepaper. available at www-03.ibm.com\/servers\/aix\/whitepapers\/multiple_page.html  Hepkin D. Guide to Multiple Page Size Support on AIX 5L Version 5.3 . IBM whitepaper. available at www-03.ibm.com\/servers\/aix\/whitepapers\/multiple_page.html"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.1289290"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/511334.511351"},{"volume-title":"IBM Journal of Research and Development.","author":"Mackerras P.","key":"e_1_2_1_6_1","unstructured":"Mackerras , P. , Matthews , T. S. , and Swanberg , R. C . Operating system exploitation of the POWER5 system , IBM Journal of Research and Development. Vol. 49 , No. 4\/5, 2005. Mackerras, P., Matthews, T. S., and Swanberg, R. C. Operating system exploitation of the POWER5 system, IBM Journal of Research and Development. Vol. 49, No. 4\/5, 2005."},{"key":"e_1_2_1_7_1","volume-title":"A. Workload Characterization for the Design of Future Servers. Proceedings of IEEE International Workload Characterization Symposium (IISWC)","author":"Maron B.","year":"2005","unstructured":"Maron , B. , Chen , T. , Vianney , D. , Olszewski , B. , Kunkel S. , Mericas , A. Workload Characterization for the Design of Future Servers. Proceedings of IEEE International Workload Characterization Symposium (IISWC) , 2005 . Maron, B., Chen, T., Vianney, D., Olszewski, B., Kunkel S., Mericas, A. Workload Characterization for the Design of Future Servers. Proceedings of IEEE International Workload Characterization Symposium (IISWC), 2005."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1060289.1060299"},{"volume-title":"POWER5 system microarchitecture. IBM Journal of Research and Development","author":"Sinharoy B.","key":"e_1_2_1_9_1","unstructured":"Sinharoy , B. , Kalla , R. N. , Tendler , J. M. , Eickemeyer , R. J. , and Joyner , J. B . POWER5 system microarchitecture. IBM Journal of Research and Development , Vol. 49 , No. 4\/5, 2005 Sinharoy, B., Kalla, R. N., Tendler, J. M., Eickemeyer, R. J., and Joyner, J. B. POWER5 system microarchitecture. IBM Journal of Research and Development, Vol. 49, No. 4\/5, 2005"},{"key":"e_1_2_1_10_1","unstructured":"See  the Search program page archived at http:\/\/www.spec.org\/cpu2005\/search  See the Search program page archived at http:\/\/www.spec.org\/cpu2005\/search"},{"key":"e_1_2_1_11_1","unstructured":"See  the documentation of utility programs for CPU2006 www.spec.org\/cpu2006\/Docs\/utility.html  See the documentation of utility programs for CPU2006 www.spec.org\/cpu2006\/Docs\/utility.html"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1241601.1241620","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1241601.1241620","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:51:26Z","timestamp":1750258286000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1241601.1241620"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3]]},"references-count":11,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2007,3]]}},"alternative-id":["10.1145\/1241601.1241620"],"URL":"https:\/\/doi.org\/10.1145\/1241601.1241620","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2007,3]]},"assertion":[{"value":"2007-03-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}