{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:45:35Z","timestamp":1772163935082,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":44,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,6,9]],"date-time":"2007-06-09T00:00:00Z","timestamp":1181347200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,6,9]]},"DOI":"10.1145\/1250662.1250680","type":"proceedings-article","created":{"date-parts":[[2007,9,14]],"date-time":"2007-09-14T12:07:37Z","timestamp":1189771657000},"page":"138-149","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":140,"title":["A novel dimensionally-decomposed router for on-chip communication in 3D architectures"],"prefix":"10.1145","author":[{"given":"Jongman","family":"Kim","sequence":"first","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}]},{"given":"Chrysostomos","family":"Nicopoulos","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}]},{"given":"Dongkook","family":"Park","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}]},{"given":"Reetuparna","family":"Das","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}]},{"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}]},{"given":"Mazin S.","family":"Yousif","sequence":"additional","affiliation":[{"name":"Intel Corp., Hillsboro, OR"}]},{"given":"Chita R.","family":"Das","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}]}],"member":"320","published-online":{"date-parts":[[2007,6,9]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"International Technology Roadmap for Semiconductors (ITRS) 2005 edition http:\/\/www.itrs.net\/.  International Technology Roadmap for Semiconductors (ITRS) 2005 edition http:\/\/www.itrs.net\/."},{"key":"e_1_3_2_1_2_1","unstructured":"Arteris http:\/\/www.arteris.com\/.  Arteris http:\/\/www.arteris.com\/."},{"key":"e_1_3_2_1_3_1","unstructured":"STMicroelectronics Spidergon http:\/\/www.st.com\/stonline\/.  STMicroelectronics Spidergon http:\/\/www.st.com\/stonline\/."},{"key":"e_1_3_2_1_4_1","unstructured":"70nm PTM technology model http:\/\/www.eas.asu.edu\/~ptm\/.  70nm PTM technology model http:\/\/www.eas.asu.edu\/~ptm\/."},{"key":"e_1_3_2_1_5_1","unstructured":"SAP Sales and Distribution Benchmark. http:\/\/www.sap.com\/solutions\/benchmark\/index.epx.  SAP Sales and Distribution Benchmark. http:\/\/www.sap.com\/solutions\/benchmark\/index.epx."},{"key":"e_1_3_2_1_6_1","unstructured":"SPECjAppServer Java Application Server Benchmark. http:\/\/www.spec.org\/jAppServer.  SPECjAppServer Java Application Server Benchmark. http:\/\/www.spec.org\/jAppServer."},{"key":"e_1_3_2_1_7_1","unstructured":"SPECjbb2005 Java Business Benchmark. http:\/\/www.spec.org\/jbb2005.  SPECjbb2005 Java Business Benchmark. http:\/\/www.spec.org\/jbb2005."},{"key":"e_1_3_2_1_8_1","unstructured":"TPC-C Design Document. http:\/\/www.tpc.org\/tpcc\/.  TPC-C Design Document. http:\/\/www.tpc.org\/tpcc\/."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"e_1_3_2_1_12_1","volume-title":"Design of High-Performance Microprocessor Circuits","author":"Chandrakasan A.","year":"2001","unstructured":"A. Chandrakasan , W.J. Bowhill , and F. Fox . Design of High-Performance Microprocessor Circuits . IEEE Press , 2001 . A. Chandrakasan, W.J. Bowhill, and F. Fox. Design of High-Performance Microprocessor Circuits. IEEE Press, 2001."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/1129601.1129707"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.127260"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01660031"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_17_1","volume-title":"Morgan Kaufmann","author":"Dally W.J.","year":"2003","unstructured":"W.J. Dally and B. Towles . Principles and Practices of Interconnection Networks . Morgan Kaufmann , 2003 . W.J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2005.1499971"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.250114"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.27"},{"key":"e_1_3_2_1_22_1","first-page":"141","volume-title":"Proceedings of The Symposium on Hot Interconnects","author":"Galles M.","year":"1996","unstructured":"M. Galles . Scalable pipelined interconnect for distributed endpoint routing: The SGI Spider chip . In Proceedings of The Symposium on Hot Interconnects , pages 141 -- 146 , 1996 . M. Galles. Scalable pipelined interconnect for distributed endpoint routing: The SGI Spider chip. In Proceedings of The Symposium on Hot Interconnects, pages 141--146, 1996."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009873"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077692"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/CMPCON.1993.289660"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168873"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.35"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.6"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.34"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.18"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.134"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_35_1","volume-title":"Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)","author":"Marculescu R.","year":"2003","unstructured":"R. Marculescu . Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03) , 2003 . R. Marculescu. Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003."},{"key":"e_1_3_2_1_36_1","volume-title":"Low-Latency Virtual-Channel Routers for On-Chip Networks. In ISCA'04: Proceedings of The 31st Annual International Symposium on Computer Architecture","author":"Mullins R.","year":"2004","unstructured":"R. Mullins , A. West , and S. Moore . Low-Latency Virtual-Channel Routers for On-Chip Networks. In ISCA'04: Proceedings of The 31st Annual International Symposium on Computer Architecture , June 2004 . R. Mullins, A. West, and S. Moore. Low-Latency Virtual-Channel Routers for On-Chip Networks. In ISCA'04: Proceedings of The 31st Annual International Symposium on Computer Architecture, June 2004."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168890"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.5555\/645461.654575"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876446"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.65"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0743-7315(03)00009-1"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.35"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.138"}],"event":{"name":"SPAA07: 19th ACM Symposium on Parallelism in Algorithms and Architectures","location":"San Diego California USA","acronym":"SPAA07","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS Computer Society"]},"container-title":["Proceedings of the 34th annual international symposium on Computer architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1250662.1250680","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1250662.1250680","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:18Z","timestamp":1750243938000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1250662.1250680"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,6,9]]},"references-count":44,"alternative-id":["10.1145\/1250662.1250680","10.1145\/1250662"],"URL":"https:\/\/doi.org\/10.1145\/1250662.1250680","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1273440.1250680","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2007,6,9]]},"assertion":[{"value":"2007-06-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}