{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,4]],"date-time":"2026-04-04T06:13:11Z","timestamp":1775283191586,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,6,9]],"date-time":"2007-06-09T00:00:00Z","timestamp":1181347200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,6,9]]},"DOI":"10.1145\/1250662.1250681","type":"proceedings-article","created":{"date-parts":[[2007,9,14]],"date-time":"2007-09-14T12:07:37Z","timestamp":1189771657000},"page":"150-161","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":213,"title":["Express virtual channels"],"prefix":"10.1145","author":[{"given":"Amit","family":"Kumar","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li-Shiuan","family":"Peh","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Partha","family":"Kundu","sequence":"additional","affiliation":[{"name":"Intel Corp., Santa Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,6,9]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"\"International Technology Roadmap for Semiconductors \" http:\/\/public.itrs.net.  \"International Technology Roadmap for Semiconductors \" http:\/\/public.itrs.net."},{"key":"e_1_3_2_1_2_1","volume-title":"The future of wires,\" Proc","author":"Ho R.","unstructured":"R. Ho , K. Mai , and M. Horowitz , \" The future of wires,\" Proc . IEEE , vol. 89 , no. 4, Apr. 2001. R. Ho, K. Mai, and M. Horowitz, \"The future of wires,\" Proc. IEEE, vol. 89, no. 4, Apr. 2001."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"e_1_3_2_1_4_1","volume-title":"Int. Symp. Computer Architecture","author":"Taylor M. B.","year":"2004","unstructured":"M. B. Taylor : An exposed-wire-delay architecture for ILP and streams,\" in Proc . Int. Symp. Computer Architecture , June 2004 . M. B. Taylor et al., \"Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams,\" in Proc. Int. Symp. Computer Architecture, June 2004."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"issue":"4","key":"e_1_3_2_1_7_1","article-title":"Introduction to the Cell multiprocessor","volume":"49","author":"Kahle J. A.","year":"2005","unstructured":"J. A. Kahle , \" Introduction to the Cell multiprocessor ,\" IBM Journal of Research and Development , vol. 49 , no. 4\/5 , 2005 . J. A. Kahle et al., \"Introduction to the Cell multiprocessor,\" IBM Journal of Research and Development, vol. 49, no. 4\/5, 2005.","journal-title":"IBM Journal of Research and Development"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379045"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325115"},{"key":"e_1_3_2_1_10_1","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally W. J.","year":"2004","unstructured":"W. J. Dally and B. Towles , Principles and Practices of Interconnection Networks . Morgan Kaufmann Publishers , 2004 . W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, 2004."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.83652"},{"key":"e_1_3_2_1_12_1","first-page":"188","volume-title":"Int. Symp. Computer Architecture","author":"Mullins R.","year":"2004","unstructured":"R. Mullins , A. West , and S. Moore , \" Low-latency virtual-channel routers for on-chip networks,\" in Proc . Int. Symp. Computer Architecture , June 2004 , pp. 188 -- 197 . R. Mullins, A. West, and S. Moore, \"Low-latency virtual-channel routers for on-chip networks,\" in Proc. Int. Symp. Computer Architecture, June 2004, pp. 188--197."},{"key":"e_1_3_2_1_13_1","first-page":"255","volume-title":"Int. Symp. High Performance Computer Architecture","author":"Peh L.-S.","year":"2001","unstructured":"L.-S. Peh and W. J. Dally , \" A delay model and speculative architecture for pipelined routers,\" in Proc . Int. Symp. High Performance Computer Architecture , Jan. 2001 , pp. 255 -- 266 . L.-S. Peh and W. J. Dally, \"A delay model and speculative architecture for pipelined routers,\" in Proc. Int. Symp. High Performance Computer Architecture, Jan. 2001, pp. 255--266."},{"key":"e_1_3_2_1_14_1","unstructured":"\"SPLASH-2 \" http:\/\/www-ash.stanford.edu\/apps\/SPLASH\/.  \"SPLASH-2 \" http:\/\/www-ash.stanford.edu\/apps\/SPLASH\/."},{"key":"e_1_3_2_1_15_1","first-page":"141","article-title":"Scalable pipelined interconnect for distributed endpoint routing: The SGI SPIDER chip","volume":"4","author":"Galles M.","year":"1996","unstructured":"M. Galles , \" Scalable pipelined interconnect for distributed endpoint routing: The SGI SPIDER chip .\" in Proc. Hot Interconnects 4 , Aug. 1996 , pp. 141 -- 146 . M. Galles, \"Scalable pipelined interconnect for distributed endpoint routing: The SGI SPIDER chip.\" in Proc. Hot Interconnects 4, Aug. 1996, pp. 141--146.","journal-title":"Proc. Hot Interconnects"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.988687"},{"key":"e_1_3_2_1_17_1","first-page":"105","volume-title":"Int. Symp. Microarchitecture","author":"Wang H.-S.","year":"2003","unstructured":"H.-S. Wang , L.-S. Peh , and S. Malik , \" Power-driven design of router microarchitectures in on-chip networks,\" in Proc . Int. Symp. Microarchitecture , Nov. 2003 , pp. 105 -- 116 . H.-S. Wang, L.-S. Peh, and S. Malik, \"Power-driven design of router microarchitectures in on-chip networks,\" in Proc. Int. Symp. Microarchitecture, Nov. 2003, pp. 105--116."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009947"},{"key":"e_1_3_2_1_19_1","first-page":"294","volume-title":"Int. Symp. Microarchitecture","author":"Wang H.-S.","year":"2002","unstructured":"H.-S. Wang , : A power-performance simulator for interconnection networks,\" in Proc . Int. Symp. Microarchitecture , Nov. 2002 , pp. 294 -- 305 . H.-S. Wang, et al., \"Orion: A power-performance simulator for interconnection networks,\" in Proc. Int. Symp. Microarchitecture, Nov. 2002, pp. 294--305."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871531"},{"issue":"29","key":"e_1_3_2_1_21_1","first-page":"7","article-title":"Bochs: A portable PC emulator for Unix\/X","volume":"1996","author":"Lawton K. P.","year":"1996","unstructured":"K. P. Lawton , \" Bochs: A portable PC emulator for Unix\/X ,\" Linux J. , vol. 1996 , no. 29 , p. 7 , 1996 . K. P. Lawton, \"Bochs: A portable PC emulator for Unix\/X,\" Linux J., vol. 1996, no. 29, p. 7, 1996.","journal-title":"Linux J."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.35"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996638"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.37"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"e_1_3_2_1_26_1","first-page":"61","volume-title":"Int. Conf. Parallel Processing","author":"Duato J.","year":"1996","unstructured":"J. Duato , high performance router architecture for interconnection networks,\" in Proc . Int. Conf. Parallel Processing , Aug. 1996 , pp. 61 -- 68 . J. Duato, et al., \"A high performance router architecture for interconnection networks,\" in Proc. Int. Conf. Parallel Processing, Aug. 1996, pp. 61--68."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.382317"},{"key":"e_1_3_2_1_28_1","first-page":"73","volume-title":"Int. Symp. High Performance Computer Architecture","author":"Peh L.-S.","year":"2000","unstructured":"L.-S. Peh and W. J. Dally , \" Flit-reservation flow control,\" in Proc . Int. Symp. High Performance Computer Architecture , Jan. 2000 , pp. 73 -- 84 . L.-S. Peh and W. J. Dally, \"Flit-reservation flow control,\" in Proc. Int. Symp. High Performance Computer Architecture, Jan. 2000, pp. 73--84."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.6"}],"event":{"name":"SPAA07: 19th ACM Symposium on Parallelism in Algorithms and Architectures","location":"San Diego California USA","acronym":"SPAA07","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS Computer Society"]},"container-title":["Proceedings of the 34th annual international symposium on Computer architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1250662.1250681","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1250662.1250681","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:18Z","timestamp":1750243938000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1250662.1250681"}},"subtitle":["towards the ideal interconnection fabric"],"short-title":[],"issued":{"date-parts":[[2007,6,9]]},"references-count":29,"alternative-id":["10.1145\/1250662.1250681","10.1145\/1250662"],"URL":"https:\/\/doi.org\/10.1145\/1250662.1250681","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1273440.1250681","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2007,6,9]]},"assertion":[{"value":"2007-06-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}