{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:45:35Z","timestamp":1772163935044,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":39,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,6,9]],"date-time":"2007-06-09T00:00:00Z","timestamp":1181347200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,6,9]]},"DOI":"10.1145\/1250662.1250686","type":"proceedings-article","created":{"date-parts":[[2007,9,14]],"date-time":"2007-09-14T12:07:37Z","timestamp":1189771657000},"page":"186-197","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":175,"title":["Core fusion"],"prefix":"10.1145","author":[{"given":"Engin","family":"Ipek","sequence":"first","affiliation":[{"name":"Cornell University, Ithaca, NY"}]},{"given":"Meyrem","family":"Kirman","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY"}]},{"given":"Nevin","family":"Kirman","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY"}]},{"given":"Jose F.","family":"Martinez","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY"}]}],"member":"320","published-online":{"date-parts":[[2007,6,9]]},"reference":[{"key":"e_1_3_2_1_1_1","author":"Altschul S.","year":"1990","unstructured":"S. Altschul , W. Gish , W. Miller , E. Myers , and D. Lipman . Basic local alignment search tool. Journal of Molecular Biology, pages 403--410 , 1990 . S. Altschul, W. Gish, W. Miller, E. Myers, and D. Lipman. Basic local alignment search tool. Journal of Molecular Biology, pages 403--410, 1990.","journal-title":"Journal of Molecular Biology, pages 403--410"},{"key":"e_1_3_2_1_2_1","volume-title":"Quantitative performance analysis of the SPEC OMPM2001 benchmarks. Scientific Programming, 11(2):105--124","author":"Aslot V.","year":"2003","unstructured":"V. Aslot and R. Eigenmann . Quantitative performance analysis of the SPEC OMPM2001 benchmarks. Scientific Programming, 11(2):105--124 , 2003 . V. Aslot and R. Eigenmann. Quantitative performance analysis of the SPEC OMPM2001 benchmarks. Scientific Programming, 11(2):105--124, 2003."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.51"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859650"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360165"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300984"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859649"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/645988.674171"},{"key":"e_1_3_2_1_9_1","volume":"2","author":"Calder B.","year":"2000","unstructured":"B. Calder and G. Reinman . A comparative survey of load speculation architectures. Journal of Instruction-Level Parallelism , 2 , May 2000 . B. Calder and G. Reinman. A comparative survey of load speculation architectures. Journal of Instruction-Level Parallelism, 2, May 2000.","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/520793.825753"},{"key":"e_1_3_2_1_11_1","first-page":"132","volume-title":"Intl. Symp. on High-Performance Computer Architecture","author":"Canal R.","year":"2000","unstructured":"R. Canal , J.-M. Parcerisa , and A. Gonz\u00e1lez . Dynamic cluster assignment mechanisms . In Intl. Symp. on High-Performance Computer Architecture , pages 132 -- 142 , Toulouse, France , January 2000 . R. Canal, J.-M. Parcerisa, and A. Gonz\u00e1lez. Dynamic cluster assignment mechanisms. In Intl. Symp. on High-Performance Computer Architecture, pages 132--142, Toulouse, France, January 2000."},{"key":"e_1_3_2_1_12_1","volume-title":"Morgan Kaufmann","author":"Chandra R.","year":"2001","unstructured":"R. Chandra , L. Dagum , D. Kohr , D. Maydan , J. McDonald , and R. Menon . Parallel Programming in OpenMP . Morgan Kaufmann , San Francisco, CA , 2001 . R. Chandra, L. Dagum, D. Kohr, D. Maydan, J. McDonald, and R. Menon. Parallel Programming in OpenMP. Morgan Kaufmann, San Francisco, CA, 2001."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.12"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279378"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303010"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430566"},{"key":"e_1_3_2_1_17_1","volume-title":"IEEE Intl. Electron Devices Meeting","author":"Bai P.","year":"2005","unstructured":"P. Bai A 65nm logic technology featuring 35nm gate length, enhanced channel strain, 8 cu interconnect layers, low-k ild and 0.57m2 sram cell . In IEEE Intl. Electron Devices Meeting , Washington, DC , December 2005 . P. Bai et al. A 65nm logic technology featuring 35nm gate length, enhanced channel strain, 8 cu interconnect layers, low-k ild and 0.57m2 sram cell. In IEEE Intl. Electron Devices Meeting, Washington, DC, December 2005."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266815"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054950"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2002.8"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956569"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006707"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.34"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006254"},{"key":"e_1_3_2_1_27_1","volume-title":"IBM","author":"Lawrence R.","year":"1998","unstructured":"R. Lawrence , G. Almasi , and H. Rushmeier . A scalable parallel algorithm for self-organizing maps with applications to sparse data mining problems. Technical report , IBM , January 1998 . R. Lawrence, G. Almasi, and H. Rushmeier. A scalable parallel algorithm for self-organizing maps with applications to sparse data mining problems. Technical report, IBM, January 1998."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339673"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/774861.774863"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/255235.255288"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237140"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"e_1_3_2_1_35_1","unstructured":"J. Renau B. Fraguela J. Tuck W. Liu M. Prvulovic L. Ceze S. Sarangi P. Sack K. Strauss and P. Montesinos. http:\/\/sesc.sourceforge.net.  J. Renau B. Fraguela J. Tuck W. Liu M. Prvulovic L. Ceze S. Sarangi P. Sack K. Strauss and P. Montesinos. http:\/\/sesc.sourceforge.net."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266814"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224451"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346182"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.910816"}],"event":{"name":"SPAA07: 19th ACM Symposium on Parallelism in Algorithms and Architectures","location":"San Diego California USA","acronym":"SPAA07","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS Computer Society"]},"container-title":["Proceedings of the 34th annual international symposium on Computer architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1250662.1250686","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1250662.1250686","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:52:18Z","timestamp":1750243938000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1250662.1250686"}},"subtitle":["accommodating software diversity in chip multiprocessors"],"short-title":[],"issued":{"date-parts":[[2007,6,9]]},"references-count":39,"alternative-id":["10.1145\/1250662.1250686","10.1145\/1250662"],"URL":"https:\/\/doi.org\/10.1145\/1250662.1250686","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1273440.1250686","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2007,6,9]]},"assertion":[{"value":"2007-06-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}