{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:45:38Z","timestamp":1772163938444,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,6,13]],"date-time":"2007-06-13T00:00:00Z","timestamp":1181692800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,6,13]]},"DOI":"10.1145\/1254766.1254809","type":"proceedings-article","created":{"date-parts":[[2007,9,14]],"date-time":"2007-09-14T12:07:37Z","timestamp":1189771657000},"page":"237-247","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Compiler-managed partitioned data caches for low power"],"prefix":"10.1145","author":[{"given":"Rajiv","family":"Ravindran","sequence":"first","affiliation":[{"name":"Hewlett-Packard Company, Cupertino, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Chu","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor, MI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Scott","family":"Mahlke","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor, MI"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,6,13]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"248","volume-title":"D. Selective Cache Ways: On Demand Cache Resource Allocation. In Proc. of the 32nd Annual International Symposium on Microarchitecture (Nov.","author":"ALBONESI","year":"1999","unstructured":"ALBONESI , D. Selective Cache Ways: On Demand Cache Resource Allocation. In Proc. of the 32nd Annual International Symposium on Microarchitecture (Nov. 1999 ), pp. 248 -- 259 . ALBONESI, D. Selective Cache Ways: On Demand Cache Resource Allocation. In Proc. of the 32nd Annual International Symposium on Microarchitecture (Nov. 1999), pp. 248--259."},{"key":"e_1_3_2_1_2_1","unstructured":"AMD. Am41PDS3228D SRAM 2004.  AMD. Am41PDS3228D SRAM 2004."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360153"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/774789.774805"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/525424.822662"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/301618.301633"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337523"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313860"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/224538.224622"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383086"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313948"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/784895.785105"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822123"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSL.2003.821550"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/645989.674329"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/354880.354898"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.91.0002"},{"key":"e_1_3_2_1_20_1","first-page":"1","volume":"9","author":"MONTANARO J.","year":"1997","unstructured":"MONTANARO , J. , ET AL . A 160 M Hz , 32-b, 0.5- W CMOS RISC Microprocessor. Digital Technical Journal 9 , 1 ( 1997 ), 49--62. MONTANARO, J., ET AL. A 160 MHz, 32-b, 0.5-W CMOS RISC Microprocessor. Digital Technical Journal 9, 1 (1997), 49--62.","journal-title":"W CMOS RISC Microprocessor. Digital Technical Journal"},{"key":"e_1_3_2_1_21_1","first-page":"8","volume-title":"Proc. of the Workshop on Intelligent Memory Systems (Nov.","author":"MORITZ C.","year":"2000","unstructured":"MORITZ , C. , FRANK , M. , AND AMARASINGHE , S. Flexcache : A framework for flexible compiler generated data caching . In Proc. of the Workshop on Intelligent Memory Systems (Nov. 2000 ), pp. 8 -- 14 . MORITZ, C., FRANK, M., AND AMARASINGHE, S. Flexcache: A framework for flexible compiler generated data caching. In Proc. of the Workshop on Intelligent Memory Systems (Nov. 2000), pp. 8--14."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344526"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-27864-1_14"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.225"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.959860"},{"key":"e_1_3_2_1_26_1","first-page":"3","volume-title":"ET AL. The Split Spatial\/Non-Spatial Cache: A Performance and Complexity Evaluation. In Proc. of the IEEE TCCA Newsletter (July","author":"PRVULOVIC M.","year":"1999","unstructured":"PRVULOVIC , M. , ET AL. The Split Spatial\/Non-Spatial Cache: A Performance and Complexity Evaluation. In Proc. of the IEEE TCCA Newsletter (July 1999 ), pp. 3 -- 10 . PRVULOVIC, M., ET AL. The Split Spatial\/Non-Spatial Cache: A Performance and Complexity Evaluation. In Proc. of the IEEE TCCA Newsletter (July 1999), pp. 3--10."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/277650.277661"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1996.537156"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305158"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/INTERACT.2005.7"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305189"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086310"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:SUPE.0000014800.27383.8f"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.752656"},{"key":"e_1_3_2_1_36_1","volume-title":"An infrastructure for research in ILP","author":"TRIMARAN.","year":"2000","unstructured":"TRIMARAN. An infrastructure for research in ILP , 2000 . http:\/\/www.trimaran.org\/. TRIMARAN. An infrastructure for research in ILP, 2000. http:\/\/www.trimaran.org\/."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/225160.225177"},{"key":"e_1_3_2_1_38_1","first-page":"131","volume-title":"ET AL. The Minimax Cache: An Energy-Efficient Framework for Media Processors. In Proc. of the 8th International Symposium on High-Performance Computer Architecture (Feb.","author":"UNSAL O.S.","year":"2002","unstructured":"UNSAL , O.S. , ET AL. The Minimax Cache: An Energy-Efficient Framework for Media Processors. In Proc. of the 8th International Symposium on High-Performance Computer Architecture (Feb. 2002 ), pp. 131 -- 141 . UNSAL, O.S., ET AL. The Minimax Cache: An Energy-Efficient Framework for Media Processors. In Proc. of the 8th International Symposium on High-Performance Computer Architecture (Feb. 2002), pp. 131--141."},{"key":"e_1_3_2_1_39_1","first-page":"124","volume-title":"K. Direct Addressed Caches for Reduced Power Consumption. In Proc. of the 34th Annual International Symposium on Microarchitecture (Dec.","author":"WITCHEL E.","year":"2001","unstructured":"WITCHEL , E. , LARSEN , S. , ANANIAN , S. , AND ASANOVIC , K. Direct Addressed Caches for Reduced Power Consumption. In Proc. of the 34th Annual International Symposium on Microarchitecture (Dec. 2001 ), pp. 124 -- 133 . WITCHEL, E., LARSEN, S., ANANIAN, S., AND ASANOVIC, K. Direct Addressed Caches for Reduced Power Consumption. In Proc. of the 34th Annual International Symposium on Microarchitecture (Dec. 2001), pp. 124--133."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.5555\/874076.876488"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.12"},{"key":"e_1_3_2_1_42_1","first-page":"504","volume-title":"Proc. of the 1997 International Conference on Computer Design","author":"ZHANG C.","year":"1997","unstructured":"ZHANG , C. , ZHANG , X. , AND YAN , Y. Multi-column implementations for cache associativity . In Proc. of the 1997 International Conference on Computer Design ( 1997 ), pp. 504 -- 509 . ZHANG, C., ZHANG, X., AND YAN, Y. Multi-column implementations for cache associativity. In Proc. of the 1997 International Conference on Computer Design (1997), pp. 504--509."}],"event":{"name":"LCTES 07: ACM SIGBED-SIGPLAN Conference on Languages, Compilers and Tools for Embedded Systems","location":"San Diego California USA","acronym":"LCTES 07","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGARCH ACM Special Interest Group on Computer Architecture","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 2007 ACM SIGPLAN\/SIGBED conference on Languages, compilers, and tools for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1254766.1254809","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1254766.1254809","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T10:47:43Z","timestamp":1750243663000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1254766.1254809"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,6,13]]},"references-count":40,"alternative-id":["10.1145\/1254766.1254809","10.1145\/1254766"],"URL":"https:\/\/doi.org\/10.1145\/1254766.1254809","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1273444.1254809","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2007,6,13]]},"assertion":[{"value":"2007-06-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}