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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2007,8,17]]},"abstract":"<jats:p>\n            Parameter variations, noise susceptibility, and increasing energy dissipation of cmos devices have been recognized as major challenges in circuit and microarchitecture design in the nanometer regime. Among these, parameter variations and noise susceptibility are increasingly causing cmos devices to behave in an \u201cunreliable\u201d or \u201cprobabilistic\u201d manner. To address these challenges, a shift in design paradigm from current-day deterministic designs to \u201cstatistical\u201d or \u201cprobabilistic\u201d designs is deemed inevitable. To respond to this need, in this article, we introduce and study an entirely novel family of probabilistic architectures: the\n            <jats:italic>probabilistic system-on-a-chip<\/jats:italic>\n            (psoc). psoc architectures are based on cmos devices rendered probabilistic due to noise, referred to as\n            <jats:italic>probabilistic<\/jats:italic>\n            CMOS or PCMOS devices. We demonstrate that in addition to harnessing the probabilistic behavior of pcmos devices, psoc architectures yield significant improvements, both in energy consumed as well as performance in the context of probabilistic or randomized applications with broad utility. All of our application and architectural savings are quantified using the product of the energy and performance, denoted (energy \u00d7 performance): The pcmos-based gains are as high as a substantial multiplicative factor of over 560 when compared to a competing energy-efficient cmos-based realization. Our architectural design is application specific and involves navigating design space spanning the algorithm (application), its architecture (psoc), and the probabilistic technology (pcmos).\n          <\/jats:p>","DOI":"10.1145\/1255456.1255466","type":"journal-article","created":{"date-parts":[[2007,9,14]],"date-time":"2007-09-14T13:44:55Z","timestamp":1189777495000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["Probabilistic system-on-a-chip architectures"],"prefix":"10.1145","volume":"12","author":[{"given":"Lakshmi N.","family":"Chakrapani","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pinar","family":"Korkmaz","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bilge E. 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