{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:52:41Z","timestamp":1750308761952,"version":"3.41.0"},"reference-count":16,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2007,8,17]],"date-time":"2007-08-17T00:00:00Z","timestamp":1187308800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004725","name":"Ministry of Economic Affairs","doi-asserted-by":"publisher","award":["96-EC-17-A-01-S1-038"],"award-info":[{"award-number":["96-EC-17-A-01-S1-038"]}],"id":[{"id":"10.13039\/501100004725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001868","name":"National Science Council Taiwan","doi-asserted-by":"publisher","award":["NSC-95-2220-E-007-003NSC-95-2220-E-007-019"],"award-info":[{"award-number":["NSC-95-2220-E-007-003NSC-95-2220-E-007-019"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2007,8,17]]},"abstract":"<jats:p>Multithreshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption. Sleep transistor sizing is the key issue when a MTCMOS circuit is designed. If the size of sleep transistor is large enough, the circuit performance can surely be maintained but the area and dynamic power consumption of the sleep transistor may increase. On the other hand, if the sleep transistor size is too small, there will be significant performance degradation because of the increased resistance to ground. Previous approaches [Kao et al. 1998; Anis et al. 2002] to designing sleep transistor size are based mainly on mutually-exclusive discharge patterns. However, these approaches considered only the topology of a circuit (i.e., interconnections of nodes in the circuit-graph saving the functionality of node). We observed that any two possible simultaneously switching gates may not discharge at the same time in terms of functionality. Thus, we propose an algorithm to determine how to cluster cells to share sleep transistors, while taking both topology and functionality into consideration. Moreover, one placement refinement algorithm that takes clustering information into account will be presented. At the logic level, the results show that the proposed clustering method can achieve an average of 22% reduction in terms of the number of unit-size sleep transistors as compared to a method that does not consider functionality. At the physical level, two placement results are discussed. The first is produced by a traditional placement tool plus topology check (functionality check) for insertion of sleep transistors. It shows that the functionality check algorithm produces 9% less chip area as compared with the topology check algorithm. The second result is produced by a placement refinement algorithm where the initial placement is done in the first placement experiment. It shows that the placement refinement algorithm achieves 5% more reduction in area at the expense of 4% increase in wire length. Totally, around 14% reduction is achieved by utilizing the clustering information.<\/jats:p>","DOI":"10.1145\/1255456.1255467","type":"journal-article","created":{"date-parts":[[2007,9,14]],"date-time":"2007-09-14T13:44:55Z","timestamp":1189777495000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A functionality-directed clustering technique for low-power MTCMOS design\u2014computation of simultaneously discharging current"],"prefix":"10.1145","volume":"12","author":[{"given":"Ang-Chih","family":"Hsieh","sequence":"first","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan, R. O. C."}]},{"given":"Tzu-Teng","family":"Lin","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan, R. O. C."}]},{"given":"Tsuang-Wei","family":"Chang","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan, R. O. C."}]},{"given":"Tingting","family":"Hwang","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan, R. O. C."}]}],"member":"320","published-online":{"date-parts":[[2008,5,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514041"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370356"},{"key":"e_1_2_1_3_1","unstructured":"BSIM3. 2007. BSIM3 homepage. http:\/\/www-device.eecs.berkeley.edu~bsim3\/arch_ftp.html.  BSIM3. 2007. BSIM3 homepage. http:\/\/www-device.eecs.berkeley.edu~bsim3\/arch_ftp.html."},{"key":"e_1_2_1_4_1","unstructured":"Gerez S. H. 1997. Algorithms for VLSI Design Automation. John Wiley &amp; Sons New York.   Gerez S. H. 1997. Algorithms for VLSI Design Automation. John Wiley &amp; Sons New York."},{"volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC). 205--208","author":"Ho Y.-T.","key":"e_1_2_1_5_1"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774593"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277180"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266182"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.402499"},{"volume-title":"Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe (DATE). 494--499","author":"Lee D.","key":"e_1_2_1_10_1"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775881"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775879"},{"key":"e_1_2_1_13_1","first-page":"8","article-title":"1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS","volume":"30","author":"Muth S.","year":"1995","journal-title":"IEEE J. Solid-State Circ."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009963"},{"volume-title":"Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD). 260--263","author":"Wang M.","key":"e_1_2_1_15_1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871536"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1255456.1255467","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1255456.1255467","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:22:28Z","timestamp":1750278148000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1255456.1255467"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8,17]]},"references-count":16,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2007,8,17]]}},"alternative-id":["10.1145\/1255456.1255467"],"URL":"https:\/\/doi.org\/10.1145\/1255456.1255467","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2007,8,17]]},"assertion":[{"value":"2005-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2007-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-05-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}