{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:52:35Z","timestamp":1750308755479,"version":"3.41.0"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2007,7,1]],"date-time":"2007-07-01T00:00:00Z","timestamp":1183248000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2007,7]]},"abstract":"<jats:p>The continual decrease in transistor size (through either scaled CMOS or emerging nanotechnologies) promises to usher in an era of tera to peta-scale integration but with increasing defects. Regardless of fabrication methodology (top-down or bottom-up), defect-tolerant architectures are necessary to exploit the full potential of future increased device densities.<\/jats:p>\n          <jats:p>This article explores a defect-tolerant SIMD architecture (SOSA) that self-organizes a large number of limited capability nodes with high defect rates into SIMD processing elements. Simulation results show that SOSA matches or exceeds the performance of conventional systems for moderate to large problems, but with lower power density.<\/jats:p>","DOI":"10.1145\/1265949.1265956","type":"journal-article","created":{"date-parts":[[2007,9,14]],"date-time":"2007-09-14T13:44:55Z","timestamp":1189777495000},"page":"10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A self-organizing defect tolerant SIMD architecture"],"prefix":"10.1145","volume":"3","author":[{"given":"Jaidev","family":"Patwardhan","sequence":"first","affiliation":[{"name":"MIPS Technologies"}]},{"given":"Chris","family":"Dwyer","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Duke University, Durham, NC"}]},{"given":"Alvin R.","family":"Lebeck","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Duke University, Durham, NC"}]}],"member":"320","published-online":{"date-parts":[[2007,7]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/332833.332842"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.1065824"},{"key":"e_1_2_1_4_1","doi-asserted-by":"crossref","unstructured":"Burke P. J. 2004. Carbon nanotube devices for GHz to THz applications. (SPIE) 5593 52--61.  Burke P. J. 2004. Carbon nanotube devices for GHz to THz applications. (SPIE) 5593 52--61.","DOI":"10.1117\/12.568159"},{"volume-title":"Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, 141--150","author":"Ciricescu S.","key":"e_1_2_1_5_1","unstructured":"Ciricescu , S. , Essick , R. , Lucas , B. , May , P. , Moat , K. , Norris , J. , Schuette , M. , and Saidi , A . 2003. The reconfigurable streaming vector processor (RSVP) . In Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, 141--150 . Ciricescu, S., Essick, R., Lucas, B., May, P., Moat, K., Norris, J., Schuette, M., and Saidi, A. 2003. The reconfigurable streaming vector processor (RSVP). In Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, 141--150."},{"volume-title":"Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2--10","author":"Culbertson W. B.","key":"e_1_2_1_6_1","unstructured":"Culbertson , W. B. , Amerson , R. , Carter , R. J. , Kuekes , P. , and Snider , G . 1996. The teramac custom computer: Extending the limits with defect tolerance . In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2--10 . Culbertson, W. B., Amerson, R., Carter, R. J., Kuekes, P., and Snider, G. 1996. The teramac custom computer: Extending the limits with defect tolerance. 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Annual Conference on Foundations of Nanoscience: Self-Assembled Architectures and Devices, 187--191."},{"volume-title":"Proceedings of the 29th Annual International Symposium on Computer Architecture, 281--292","author":"Espasa R.","key":"e_1_2_1_13_1","unstructured":"Espasa , R. , Ardanaz , F. , Emer , J. , Felix , S. , Gago , J. , Gramunt , R. , Hernandez , I. , Juan , T. , Lowney , G. , Mattina , M. , and Seznec , A . 2002. Tarantula: A vector extension to the alpha architecture . In Proceedings of the 29th Annual International Symposium on Computer Architecture, 281--292 . Espasa, R., Ardanaz, F., Emer, J., Felix, S., Gago, J., Gramunt, R., Hernandez, I., Juan, T., Lowney, G., Mattina, M., and Seznec, A. 2002. Tarantula: A vector extension to the alpha architecture. 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