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In this paper, we define a simulation-based methodology for extending system performance-modeling frameworks to also include power modeling. We demonstrate the use of this methodology with a case study of a real, complex embedded system, comprising the Intel XScale\u00aeg embedded microprocessor, its WMMX\u2122 SIMD coprocessor, L1 caches, SDRAM and the on-board address and data buses. We describe detailed power models for each of these components and validate them against physical measurements from hardware, demonstrating that such frameworks enable designers to model both power and performance at high speeds without sacrificing accuracy. Our results indicate that the power estimates obtained are accurate within 5% of physical measurements from hardware, while simulation speeds consistently exceed a million instructions per second (MIPS).<\/jats:p>","DOI":"10.1145\/1274858.1274864","type":"journal-article","created":{"date-parts":[[2007,9,26]],"date-time":"2007-09-26T17:18:32Z","timestamp":1190827112000},"page":"26","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Accurate and fast system-level power modeling"],"prefix":"10.1145","volume":"6","author":[{"given":"Ankush","family":"Varma","sequence":"first","affiliation":[{"name":"University of Maryland, College Park, Maryland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bruce","family":"Jacob","sequence":"additional","affiliation":[{"name":"University of Maryland, College Park, Maryland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric","family":"Debes","sequence":"additional","affiliation":[{"name":"Intel Research Labs, Santa clare, California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Igor","family":"Kozintsev","sequence":"additional","affiliation":[{"name":"Intel Research Labs, Santa clare, California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Klein","sequence":"additional","affiliation":[{"name":"Intel Research Labs, Santa clare, California"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2005.138"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1023833.1023847"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/280756.280881"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/944645.944687"},{"key":"e_1_2_1_6_1","unstructured":"Bona A. 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