{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T13:00:56Z","timestamp":1725627656044},"publisher-location":"New York, NY, USA","reference-count":37,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,6,17]]},"DOI":"10.1145\/1274971.1274991","type":"proceedings-article","created":{"date-parts":[[2010,4,6]],"date-time":"2010-04-06T22:57:04Z","timestamp":1270594624000},"page":"126-137","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Tradeoff between data-, instruction-, and thread-level parallelism in stream processors"],"prefix":"10.1145","author":[{"given":"Jung Ho","family":"Ahn","sequence":"first","affiliation":[{"name":"Hewlett-Packard Laboratories, Palo Alto, California"}]},{"given":"Mattan","family":"Erez","sequence":"additional","affiliation":[{"name":"University of Texas at Austin, Austin, Texas"}]},{"given":"William J.","family":"Dally","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, California"}]}],"member":"320","published-online":{"date-parts":[[2007,6,17]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"dissertation","author":"Ahn J.","year":"2007","unstructured":"J. Ahn , \"Memory and Control Organizations of Stream Processors,\" Ph.D. dissertation , Stanford University , 2007 . J. Ahn, \"Memory and Control Organizations of Stream Processors,\" Ph.D. dissertation, Stanford University, 2007."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1188455.1188540"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/359576.359579"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339696"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1015706.1015800"},{"key":"e_1_3_2_1_6_1","unstructured":"ClearSpeed \"CSX600 datasheet \" http:\/\/www.clearspeed.com\/downloads\/CSX600Processor.pdf 2005.  ClearSpeed \"CSX600 datasheet \" http:\/\/www.clearspeed.com\/downloads\/CSX600Processor.pdf 2005."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1048935.1050187"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.848475"},{"key":"e_1_3_2_1_9_1","unstructured":"Elpida Memory Inc \"512M bits XDR#8482; DRAM \" http:\/\/www.elpida.com\/pdfs\/E0643E20.pdf.  Elpida Memory Inc \"512M bits XDR#8482; DRAM \" http:\/\/www.elpida.com\/pdfs\/E0643E20.pdf."},{"key":"e_1_3_2_1_10_1","volume-title":"dissertation","author":"Erez M.","year":"2006","unstructured":"M. Erez , \" Merrimac - High-Performance and High-Efficient Scientific Computing with Streams ,\" Ph. D. dissertation , Stanford University , 2006 . M. Erez, \"Merrimac - High-Performance and High-Efficient Scientific Computing with Streams,\" Ph.D. dissertation, Stanford University, 2006."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2004.69"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.848474"},{"key":"e_1_3_2_1_13_1","first-page":"14","volume-title":"Anchorage","author":"Hrishikesh M. S.","year":"2002","unstructured":"M. S. Hrishikesh , D. Burger , N. P. Jouppi , S. W. Keckler , K. I. Farkas , and P. Shivakumar , \" The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays,\" in Proceedings of the 29th International Symposium on Computer Architecture , Anchorage , Alaska , 2002 , pp. 14 -- 24 . M. S. Hrishikesh, D. Burger, N. P. Jouppi, S. W. Keckler, K. I. Farkas, and P. Shivakumar, \"The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays,\" in Proceedings of the 29th International Symposium on Computer Architecture, Anchorage, Alaska, 2002, pp. 14--24."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10007"},{"key":"e_1_3_2_1_15_1","volume-title":"dissertation","author":"Kapasi U. J.","year":"2004","unstructured":"U. J. Kapasi , \" Conditional Techniques for Stream Processing Kernels ,\" Ph. D. dissertation , Stanford University , March 2004 . U. J. Kapasi, \"Conditional Techniques for Stream Processing Kernels,\" Ph.D. dissertation, Stanford University, March 2004."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1220582"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.918001"},{"key":"e_1_3_2_1_18_1","volume-title":"Anaheim","author":"Khailany B.","year":"2003","unstructured":"B. Khailany , W. J. Dally , S. Rixner , U. J. Kapasi , J. D. Owens , and B. Towles , \" Exploring the VLSI Scalability of Stream Processors,\" in Proceedings of the 9th Symposium on High Performance Computer Architecture , Anaheim , California , February 2003 . B. Khailany, W. J. Dally, S. Rixner, U. J. Kapasi, J. D. Owens, and B. Towles, \"Exploring the VLSI Scalability of Stream Processors,\" in Proceedings of the 9th Symposium on High Performance Computer Architecture, Anaheim, California, February 2003."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612252"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859664"},{"key":"e_1_3_2_1_21_1","first-page":"52","volume-title":"The Vector-Thread Architecture,\" in Proceedings of the 31st International Symposium on Computer Architecture","author":"Krashinsky R.","year":"2004","unstructured":"R. Krashinsky , C. Batten , M. Hampton , S. Gerding , B. Pharris , J. Casper , and K. Asanovic , \" The Vector-Thread Architecture,\" in Proceedings of the 31st International Symposium on Computer Architecture , Munich, Germany , June 2004 , pp. 52 -- 63 . R. Krashinsky, C. Batten, M. Hampton, S. Gerding, B. Pharris, J. Casper, and K. Asanovic, \"The Vector-Thread Architecture,\" in Proceedings of the 31st International Symposium on Computer Architecture, Munich, Germany, June 2004, pp. 52--63."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.5009446"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339673"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379005"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.755466"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612249"},{"key":"e_1_3_2_1_28_1","first-page":"184","volume-title":"CA","author":"Pham D.","year":"2005","unstructured":"D. Pham , , \" The Design Implementation of a First-Generation CELL Processor,\" in Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco , CA , February 2005 , pp. 184 -- 185 . D. Pham, et al., \"The Design and Implementation of a First-Generation CELL Processor,\" in Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, CA, February 2005, pp. 184--185."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"crossref","DOI":"10.1002\/0470869615","volume-title":"Video Coding for Next-generation Multimedia","author":"Richardson I. E.","year":"2003","unstructured":"I. E. Richardson , H.264 and MPEG-4 Video Compression : Video Coding for Next-generation Multimedia . John Wiley & Sons, Ltd , 2003 . I. E. Richardson, H.264 and MPEG-4 Video Compression: Video Coding for Next-generation Multimedia. John Wiley & Sons, Ltd, 2003."},{"key":"e_1_3_2_1_30_1","first-page":"375","volume-title":"Toulouse","author":"Rixner S.","year":"2000","unstructured":"S. Rixner , W. J. Dally , B. Khailany , P. Mattson , U. J. Kapasi , and J. D. Owens , \" Register Organization for Media Processing,\" in Proceedings of the 6th International Symposium on High Performance Computer Architecture , Toulouse , France , January 2000 , pp. 375 -- 386 . S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi, and J. D. Owens, \"Register Organization for Media Processing,\" in Proceedings of the 6th International Symposium on High Performance Computer Architecture, Toulouse, France, January 2000, pp. 375--386."},{"key":"e_1_3_2_1_31_1","first-page":"138","volume-title":"North Carolina","author":"Rotenberg E.","year":"1997","unstructured":"E. Rotenberg , Q. Jacobson , Y. Sazeides , and J. Smith , \" Trace Processors,\" in Proceedings of the 30th ACM\/IEEE International Symposium on Microarchitecture , North Carolina , 1997 , pp. 138 -- 148 . E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith, \"Trace Processors,\" in Proceedings of the 30th ACM\/IEEE International Symposium on Microarchitecture, North Carolina, 1997, pp. 138--148."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224451"},{"key":"e_1_3_2_1_34_1","first-page":"8","article-title":"The Internet Streaming SIMD Extensions","author":"Thakkar S. T.","year":"1999","unstructured":"S. T. Thakkar and T. Huff , \" The Internet Streaming SIMD Extensions ,\" Intel Technology Journal, no. Q2 , p. 8 , May 1999 . S. T. Thakkar and T. Huff, \"The Internet Streaming SIMD Extensions,\" Intel Technology Journal, no. Q2, p. 8, May 1999.","journal-title":"Q2"},{"key":"e_1_3_2_1_35_1","first-page":"179","volume-title":"Grenoble","author":"Thies W.","year":"2002","unstructured":"W. Thies , M. Karczmarek , and S. P. Amarasinghe , \" StreamIt: A Language for Streaming Applications,\" in Proceedings of the 11th International Conference on Compiler Construction , Grenoble , France , April 2002 , pp. 179 -- 196 . W. Thies, M. Karczmarek, and S. P. Amarasinghe, \"StreamIt: A Language for Streaming Applications,\" in Proceedings of the 11th International Conference on Compiler Construction, Grenoble, France, April 2002, pp. 179--196."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224449"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612254"}],"event":{"name":"ICS07: International Conference on Supercomputing","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Seattle Washington","acronym":"ICS07"},"container-title":["Proceedings of the 21st annual international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1274971.1274991","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,11]],"date-time":"2023-01-11T15:09:42Z","timestamp":1673449782000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1274971.1274991"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,6,17]]},"references-count":37,"alternative-id":["10.1145\/1274971.1274991","10.1145\/1274971"],"URL":"https:\/\/doi.org\/10.1145\/1274971.1274991","relation":{},"subject":[],"published":{"date-parts":[[2007,6,17]]},"assertion":[{"value":"2007-06-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}