{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:08:29Z","timestamp":1758892109731},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,6,17]]},"DOI":"10.1145\/1274971.1275002","type":"proceedings-article","created":{"date-parts":[[2010,4,7]],"date-time":"2010-04-07T02:57:04Z","timestamp":1270609024000},"page":"222-231","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Increasing cache capacity through word filtering"],"prefix":"10.1145","author":[{"given":"Prateek","family":"Pujara","sequence":"first","affiliation":[{"name":"State University of New York, Binghamton, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aneesh","family":"Aggarwal","sequence":"additional","affiliation":[{"name":"State University of New York, Binghamton, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,6,17]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300984"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232983"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956539"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/139669.139725"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263631"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/800015.808178"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/225160.225175"},{"key":"e_1_3_2_1_9_1","volume-title":"Proc. HPCA","author":"Inoue K.","year":"1999","unstructured":"K. Inoue , et. al., Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM\/Logic LS Is , Proc. HPCA , 1999 . K. Inoue, et. al., Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM\/Logic LSIs, Proc. HPCA, 1999."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264213"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266806"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279404"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/52400.52407"},{"key":"e_1_3_2_1_14_1","volume-title":"Compiler-directed Cache Line Size Adaptivity","author":"Nicolaescu D.","year":"2000","unstructured":"D. Nicolaescu , et. al ., Compiler-directed Cache Line Size Adaptivity , IMS , 2000 . D. Nicolaescu, et. al., Compiler-directed Cache Line Size Adaptivity, IMS, 2000."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325135"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192072"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.5009537"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305188"},{"key":"e_1_3_2_1_19_1","volume-title":"Proc. ISCA-28","author":"Witchel E.","year":"2001","unstructured":"E. Witchel and K. Asanovic , The Span Cache: Software Controlled Tag Checks and Cache Line Size , Proc. ISCA-28 , 2001 . E. Witchel and K. Asanovic, The Span Cache: Software Controlled Tag Checks and Cache Line Size, Proc. ISCA-28, 2001."},{"key":"e_1_3_2_1_20_1","volume-title":"Proc. Int'l Symp. on VLSI","author":"Zhang C.","year":"2003","unstructured":"C. Zhang , et. al., Energy Benefits of a Configurable Line Size Cache for Embedded Systems , Proc. Int'l Symp. on VLSI , 2003 . C. Zhang, et. al., Energy Benefits of a Configurable Line Size Cache for Embedded Systems, Proc. Int'l Symp. on VLSI, 2003."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10010"},{"key":"e_1_3_2_1_22_1","volume-title":"CACTI 3.0: An Integrated Cache timing, Power, and Area Model","author":"P. Shivakumar","year":"2002","unstructured":"P. Shivakumar et al , CACTI 3.0: An Integrated Cache timing, Power, and Area Model , Technical Report , DEC Western Lab , 2002 . P. Shivakumar et al, CACTI 3.0: An Integrated Cache timing, Power, and Area Model, Technical Report, DEC Western Lab, 2002."},{"key":"e_1_3_2_1_23_1","volume-title":"Proc. IEEE Int'l SOC Conference","author":"Ghose M.","year":"2004","unstructured":"M. Ghose , et. al., CoolPression - A Hybrid Significance Compression Technique for Reducing Energy in Caches , Proc. IEEE Int'l SOC Conference , 2004 . M. Ghose, et. al., CoolPression - A Hybrid Significance Compression Technique for Reducing Energy in Caches, Proc. IEEE Int'l SOC Conference, 2004."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360150"},{"key":"e_1_3_2_1_25_1","volume-title":"Workshop on Solving the Memory Wall Problem","author":"Abali B.","year":"2000","unstructured":"B. Abali and H. Franke , Operating System Support for Fast Hardware Compression of Main Memory Contents , Workshop on Solving the Memory Wall Problem , 2000 . B. Abali and H. Franke, Operating System Support for Fast Hardware Compression of Main Memory Contents, Workshop on Solving the Memory Wall Problem, 2000."},{"key":"e_1_3_2_1_26_1","volume-title":"Proc. ISCA-31","author":"Alaa","year":"2004","unstructured":"Alaa R. Alameldeen and David A. Wood, Adaptive Cache Compression for High-Performance Processors , Proc. ISCA-31 , 2004 . Alaa R. Alameldeen and David A. Wood, Adaptive Cache Compression for High-Performance Processors, Proc. ISCA-31, 2004."},{"key":"e_1_3_2_1_27_1","volume-title":"Workshop on Solving the Memory Wall Problem","author":"Benveniste C.","year":"2000","unstructured":"C. Benveniste , et. al., Cache-Memory Interfaces in Compressed Memory Systems , Workshop on Solving the Memory Wall Problem , 2000 . C. Benveniste, et. al., Cache-Memory Interfaces in Compressed Memory Systems, Workshop on Solving the Memory Wall Problem, 2000."},{"key":"e_1_3_2_1_28_1","volume-title":"A Dynamically Partitionable Compressed Cache","author":"Chen D.","year":"2003","unstructured":"D. Chen , et. al ., A Dynamically Partitionable Compressed Cache , Singapore-MIT Alliance Symp , 2003 . D. Chen, et. al., A Dynamically Partitionable Compressed Cache, Singapore-MIT Alliance Symp, 2003."},{"key":"e_1_3_2_1_29_1","volume-title":"Proc. Data Compression Conference","author":"Franaszek P.","year":"1996","unstructured":"P. Franaszek , et. al., Parallel Compression with Cooperative Dictionary Construction , Proc. Data Compression Conference , 1996 . P. Franaszek, et. al., Parallel Compression with Cooperative Dictionary Construction, Proc. Data Compression Conference, 1996."},{"key":"e_1_3_2_1_31_1","volume-title":"Workshop on Memory Performance Issues","author":"Kim N.","year":"2002","unstructured":"N. Kim , et. al., Low-Energy Data Cache using Sign Compression and Cache Line Bisection , Workshop on Memory Performance Issues , 2002 . N. Kim, et. al., Low-Energy Data Cache using Sign Compression and Cache Line Bisection, Workshop on Memory Performance Issues, 2002."},{"key":"e_1_3_2_1_32_1","volume-title":"Proc. EUROMICRO Conference","author":"Kjelso M.","year":"1996","unstructured":"M. Kjelso , et. al., Design and Performance of a Main Memory Hardware Data Compressor , Proc. EUROMICRO Conference , 1996 . M. Kjelso, et. al., Design and Performance of a Main Memory Hardware Data Compressor, Proc. EUROMICRO Conference, 1996."},{"key":"e_1_3_2_1_33_1","volume-title":"Proc. ICCD","author":"Lee J.","year":"1999","unstructured":"J. Lee , et. al., Design and Evaluation of a Selective Compressed Memory System , Proc. ICCD , 1999 . J. Lee, et. al., Design and Evaluation of a Selective Compressed Memory System, Proc. ICCD, 1999."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(00)00030-8"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1080\/1206212X.2003.11441690"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360154"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379235"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.94"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346202"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"e_1_3_2_1_42_1","volume-title":"Proc. HPCA","author":"P. Pujara","year":"2006","unstructured":"P. Pujara et al., Increasing the Cache Efficiency by Eliminating Noise , Proc. HPCA , 2006 . P. Pujara et al., Increasing the Cache Efficiency by Eliminating Noise, Proc. HPCA, 2006."}],"event":{"name":"ICS07: International Conference on Supercomputing","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Seattle Washington","acronym":"ICS07"},"container-title":["Proceedings of the 21st annual international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1274971.1275002","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,11]],"date-time":"2023-01-11T20:09:53Z","timestamp":1673467793000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1274971.1275002"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,6,17]]},"references-count":40,"alternative-id":["10.1145\/1274971.1275002","10.1145\/1274971"],"URL":"https:\/\/doi.org\/10.1145\/1274971.1275002","relation":{},"subject":[],"published":{"date-parts":[[2007,6,17]]},"assertion":[{"value":"2007-06-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}