{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:39:37Z","timestamp":1750307977103,"version":"3.41.0"},"publisher-location":"New York, New York, USA","reference-count":16,"publisher":"ACM Press","license":[{"start":{"date-parts":[[1995,1,1]],"date-time":"1995-01-01T00:00:00Z","timestamp":788918400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1995]]},"DOI":"10.1145\/1275165.1275174","type":"proceedings-article","created":{"date-parts":[[2016,3,25]],"date-time":"2016-03-25T12:48:51Z","timestamp":1458910131000},"page":"9-es","source":"Crossref","is-referenced-by-count":0,"title":["Evaluating the performance of dynamic branch prediction schemes with BPSim"],"prefix":"10.1145","author":[{"given":"Norman","family":"Lam","sequence":"first","affiliation":[{"name":"Washington State University, Pullman, WA"}]},{"given":"Si-En","family":"Chang","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}]},{"given":"Mark L.","family":"Manwaring","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}]}],"member":"320","reference":[{"key":"key-10.1145\/1275165.1275174-1","doi-asserted-by":"crossref","unstructured":"J. H. Edmondson, P. Rubinfeld, R. Preston, and V. Rajagopalan, \"Superscalar Instruction Execution in the 21164 Alpha Microprocessor,\" IEEE Micro, Vol. 15, No. 2, April 1995, pp. 33--43.","DOI":"10.1109\/40.372349"},{"key":"key-10.1145\/1275165.1275174-2","unstructured":"M. Flynn,Computer Architecture: Pipelined and Parallel Processor Design, Jones and Bartlett, Boston, 1995."},{"key":"key-10.1145\/1275165.1275174-3","unstructured":"K. Hwang,Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw-Hill, New York, 1993."},{"key":"key-10.1145\/1275165.1275174-4","unstructured":"J. L. Hennessy and D. A. Patterson,Computer Architecture: A Quantitative Approach, 2nd Ed., Morgan Kaufmann, San Francisco, 1996."},{"key":"key-10.1145\/1275165.1275174-5","unstructured":"M. Johnson,Superscalar Microprocessor Design, Prentice Hall, Englewood Cliffs, 1991."},{"key":"key-10.1145\/1275165.1275174-6","doi-asserted-by":"crossref","unstructured":"J. Lee and A. Smith, \"Branch Prediction Strategies and Branch Target Buffer Design,\" Computer, 17(1), Jan. 1984, pp. 6--22.","DOI":"10.1109\/MC.1984.1658927"},{"key":"key-10.1145\/1275165.1275174-7","unstructured":"S. McFarling, \"Combining Branch Predictors,\" WRL Technical Note TN-36, Digital Equipment Corp., June 1993."},{"key":"key-10.1145\/1275165.1275174-8","doi-asserted-by":"crossref","unstructured":"R. Nair, \"Optimal 2-Bit Branch Predictors,\" IEEE Transactions on Computers, Vol. 44, No. 5, May 1995, pp. 698--702.","DOI":"10.1109\/12.381956"},{"key":"key-10.1145\/1275165.1275174-9","doi-asserted-by":"crossref","unstructured":"S. Pan, K. So, and J. Rahmeh, \"Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation,\" Proc. 5th Annual Intl. Conf. On Architectural Support for Prog. Lang. And O. S., Oct. 1992, pp. 76--84.","DOI":"10.1145\/143365.143490"},{"key":"key-10.1145\/1275165.1275174-10","doi-asserted-by":"crossref","unstructured":"D. B. Papworth, \"Tuning the Pentium Pro Microarchitecture,\" IEEE Micro, Vol. 16, No. 2, April 1996, pp. 8--15.","DOI":"10.1109\/40.491458"},{"key":"key-10.1145\/1275165.1275174-11","unstructured":"M. Smith,Tracing with Pixie, Technical Report CSL-TR-91-497, Stanford University, CA 9430--4055, Nov. 1991."},{"key":"key-10.1145\/1275165.1275174-12","doi-asserted-by":"crossref","unstructured":"Perleberg, C. and Smith, A. J., \"Branch Target Buffer Design and Optimization.\" IEEE Trans. On Computers, Vol. 42, No. 4, April 1993, pp. 396--412.","DOI":"10.1109\/12.214687"},{"key":"key-10.1145\/1275165.1275174-13","unstructured":"J. Smith, \"A Study of Branch Prediction Strategies,\" Proc. 8th Annual Intl. Symp. On Computer Architecture, June 1981, pp. 135--148."},{"key":"key-10.1145\/1275165.1275174-14","doi-asserted-by":"crossref","unstructured":"K C. Yeager, \"The MIPS R10000 Superscalar Microprocessor,\" IEEE Micro, Vol. 16, No. 2, April 1996, pp. 28--40.","DOI":"10.1109\/40.491460"},{"key":"key-10.1145\/1275165.1275174-15","doi-asserted-by":"crossref","unstructured":"T. Yeh and Y. Patt, \"Two-Level Adaptive Training Branch Prediction,\" Proc. 24th Annual ACM\/IEEE Symp. and Workshop on Microarchitecture, Nov 1991, pp. 51--61.","DOI":"10.1145\/123465.123475"},{"key":"key-10.1145\/1275165.1275174-16","doi-asserted-by":"crossref","unstructured":"T. Yeh and Y. Patt, \"A Comparison of Dynamic Branch Predictors That Use Two Levels of Branch History,\" Proc. 20th Annual Intl. Symp. On Computer Architecture, May 1993, pp. 257--266.","DOI":"10.1145\/165123.165161"}],"event":{"name":"the 1997 workshop","start":{"date-parts":[[1997,1,1]]},"number":"WCAE-3 1997","location":"Not Known","acronym":"WCAE-3 '97"},"container-title":["Proceedings of the 1997 workshop on Computer architecture education - WCAE-3 '97"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1275165.1275174","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/dl.acm.org\/ft_gateway.cfm?id=1275174&ftid=435226&dwn=1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:58:28Z","timestamp":1750258708000},"score":1,"resource":{"primary":{"URL":"http:\/\/dl.acm.org\/citation.cfm?doid=1275165.1275174"}},"subtitle":[],"proceedings-subject":"Computer architecture education","short-title":[],"issued":{"date-parts":[[1995]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1145\/1275165.1275174","relation":{},"subject":[],"published":{"date-parts":[[1995]]}}}