{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:51:04Z","timestamp":1750308664610,"version":"3.41.0"},"publisher-location":"New York, New York, USA","reference-count":29,"publisher":"ACM Press","license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1145\/1275521.1275540","type":"proceedings-article","created":{"date-parts":[[2016,3,25]],"date-time":"2016-03-25T12:48:51Z","timestamp":1458910131000},"page":"14-es","source":"Crossref","is-referenced-by-count":1,"title":["Didactic architectures and simulator for network processor learning"],"prefix":"10.1145","author":[{"given":"Henrique Cota","family":"de Freitas","sequence":"first","affiliation":[{"name":"Pontifical Catholic University of Minas Gerais, Brazil"}]},{"given":"Carlos Augusto P. S.","family":"Martins","sequence":"additional","affiliation":[{"name":"Pontifical Catholic University of Minas Gerais, Brazil"}]}],"member":"320","reference":[{"key":"key-10.1145\/1275521.1275540-1","unstructured":"Agere System, Fast Pattern Processor (FPP) Product Brief, April 2001, http:\/\/www.agere.com"},{"key":"key-10.1145\/1275521.1275540-2","unstructured":"Buya, R., High Performance Cluster Computing, Volume 1, Prentice Hall, 1999"},{"key":"key-10.1145\/1275521.1275540-3","unstructured":"Chameleon Systems, \"CS2000 Reconfigurable Communications Processor\", Family Product Brief, 2000"},{"key":"key-10.1145\/1275521.1275540-4","unstructured":"Cisco Systems White Paper, \"The Evolution of high-end Router Architectures-Basic Scalability and Performance Considerations for Evaluating Large-Scale Router Designs\", 2001, http:\/\/www.cisco.com"},{"key":"key-10.1145\/1275521.1275540-5","unstructured":"C-Port, C5e Network Processor Product Brief, January 2002, http:\/\/www.motorola.com"},{"key":"key-10.1145\/1275521.1275540-6","doi-asserted-by":"crossref","unstructured":"D. L. Tennenhouse, J. M. Smith, W. D. Sincoskie, D. J. Wetherall, G. J. Minden, \"A Survey of Active Network Research\", IEEE Communications Magazine, Volume 35, N<sup>o<\/sup> 1, pp.80--86, 1997","DOI":"10.1109\/35.568214"},{"key":"key-10.1145\/1275521.1275540-7","unstructured":"D. Suryanarayanan, G. T. Byrd and J. Marshall, \"A Methodology and Simulator for the Study of Network Processors\", Workshop on Network Processor (NP1 at HPCA 8), Cambridge Massachusetts, February 2--6, 2002"},{"key":"key-10.1145\/1275521.1275540-8","unstructured":"EZChip Network Processors, http:\/\/www.ezchip.com"},{"key":"key-10.1145\/1275521.1275540-9","doi-asserted-by":"crossref","unstructured":"G. Memik, S. O. Memik, W. H. Mangione-Smith, \"Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic\", The 10<sup>th<\/sup> Annual IEEE Symposium on Field-Programmable Custom Computing Machines FCCM'02, Napa, California, 21--24 April, 2002","DOI":"10.1109\/FPGA.2002.1106668"},{"key":"key-10.1145\/1275521.1275540-10","doi-asserted-by":"crossref","unstructured":"H. C. Freitas, C. A. P. S. Martins, \"Processador de Rede com Suporte a Multi-protocolo e Topologias Dinâmicas\", II Workshop de Sistemas Computacionais de Alto Desempenho, WSCAD'2001, Pirenópolis - GO, Brasil, pp.31--38 (in portuguese)","DOI":"10.5753\/wscad.2001.19120"},{"key":"key-10.1145\/1275521.1275540-11","doi-asserted-by":"crossref","unstructured":"H. C. Freitas, C. A. P. S. Martins, \"R2NP: Processador de Rede RISC Reconfigurável\", III Workshop de Sistemas Computacionais de Alto Desempenho, WSCAD'2002, Vitória, ES, Brasil, pp. 60--67 (in portuguese)","DOI":"10.5753\/wscad.2002.20762"},{"key":"key-10.1145\/1275521.1275540-12","doi-asserted-by":"crossref","unstructured":"H. C. Freitas, C. A. P. S. Martins, \"Simulation Tool of Network Processor for Learning Activities\". Frontiers in Education Conference (FIE 2002), Boston, MA, USA, November 2002, Session S2F, pp.1--6","DOI":"10.1109\/FIE.2002.1158665"},{"key":"key-10.1145\/1275521.1275540-13","unstructured":"H. C. Freitas, C. A. P. S. Martins, \"NPSIM: Simulador de Processador de Rede\". XXVIII Latin-American Conference on Informatics, CLEI'2002, Montevideo, Uruguay, November 2002 (in portuguese)"},{"key":"key-10.1145\/1275521.1275540-14","doi-asserted-by":"crossref","unstructured":"I. A. Troxel, A. D. George, S. Oral, \"Design and Analysis of a Dynamically Reconfigurable Network Processor\", IEEE Conference on Local Computer Networks (LCN), Tampa, Florida, November 6--8, 2002","DOI":"10.1109\/LCN.2002.1181821"},{"key":"key-10.1145\/1275521.1275540-15","unstructured":"IBM PowerNP NP4GS3 Databook, http:\/\/www.ibm.com"},{"key":"key-10.1145\/1275521.1275540-16","unstructured":"Intel, \"IXP 1200 - Network Processor\", Datasheet, May 2000, http:\/\/www.intel.com"},{"key":"key-10.1145\/1275521.1275540-17","doi-asserted-by":"crossref","unstructured":"K. Compton, S. Hauck, \"Reconfigurable Computing: A Survey of Systems and Software\", ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171--210","DOI":"10.1145\/508352.508353"},{"key":"key-10.1145\/1275521.1275540-18","unstructured":"Lexra, NetVortex Network Communications System Multiprocessor NPU, http:\/\/www.lexra.com"},{"key":"key-10.1145\/1275521.1275540-19","unstructured":"Lucent Technologies, Building for Next Generation Network Processors, September 1999"},{"key":"key-10.1145\/1275521.1275540-20","unstructured":"Lucent Technologies, The Challenge for Next Generation Network Processors, September 10, 1999"},{"key":"key-10.1145\/1275521.1275540-21","doi-asserted-by":"crossref","unstructured":"M. Glesner, A. Kirschbaum, \"State-of-the-Art in Rapid Prototyping\", XI Brazilian Symposium on Integrated Circuit Design, SBCCI'98, Búzios, Rio de Janeiro, 1998, pp.60--65","DOI":"10.1109\/SBCCI.1998.715411"},{"key":"key-10.1145\/1275521.1275540-22","doi-asserted-by":"crossref","unstructured":"M. Iliopoulos, T. Antonakopoulos, \"Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits\", Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10<sup>th<\/sup> International Workshop, FPL 2000, Villach, Austria, August 27--30, 2000, pp. 39--47","DOI":"10.1007\/3-540-44614-1_5"},{"key":"key-10.1145\/1275521.1275540-23","unstructured":"MMC Networks, \"EPIF-105, EPIF-200, GPIF-207, XPIF-300, Packet Processors\", http:\/\/www.mmcnet.com"},{"key":"key-10.1145\/1275521.1275540-24","unstructured":"Patterson, D. A., J. L. Hennessy, Computer Organization and Design: The Hardware\/Software Interface, Morgan Kaufmann Publisher, 1997"},{"key":"key-10.1145\/1275521.1275540-25","unstructured":"Sitera IQ2000, Network Processor Product Brief, http:\/\/www.sitera.com"},{"key":"key-10.1145\/1275521.1275540-26","doi-asserted-by":"crossref","unstructured":"T. H. Medeiros, C. A. P. S. Martins, \"Reconf_KMT, Uma Ferramenta Reconfigurável para a Simulação de Microprocessadores\", III Workshop de Sistemas Computacionais de Alto Desempenho, WSCAD'2002, Vitória, ES, Brasil, pp. 32--38 (in portuguese)","DOI":"10.5753\/wscad.2002.20758"},{"key":"key-10.1145\/1275521.1275540-27","doi-asserted-by":"crossref","unstructured":"T. Wolf and J. Turner, \"Design Issues for High Performance Active Routers\", International Zurich Seminar on Broadband Communications, Zurich, Switzerland, 2000, pp. 199--205","DOI":"10.1109\/IZSBC.2000.829252"},{"key":"key-10.1145\/1275521.1275540-28","unstructured":"Tanembaum, A. S., Computer Networks, Prentice-Hall, 1996"},{"key":"key-10.1145\/1275521.1275540-29","unstructured":"W. D. Mensch. Jr. and D. A. Silage, \"System-on-chip Design Methodology in Engineering Education\", International Conference on Engineering Education, ICEE2000 (IEEE\/CS), Taipei, Taiwan, August 2000, pp. 224--228"}],"event":{"name":"the 2003 workshop","start":{"date-parts":[[2003,6,8]]},"number":"WCAE 2003","theme":"Held in conjunction with the 30th International Symposium on Computer Architecture","location":"San Diego, California","acronym":"WCAE '03"},"container-title":["Proceedings of the 2003 workshop on Computer architecture education Held in conjunction with the 30th International Symposium on Computer Architecture - WCAE '03"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1275521.1275540","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/dl.acm.org\/ft_gateway.cfm?id=1275540&ftid=435644&dwn=1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T20:00:31Z","timestamp":1750276831000},"score":1,"resource":{"primary":{"URL":"http:\/\/dl.acm.org\/citation.cfm?doid=1275521.1275540"}},"subtitle":[],"proceedings-subject":"Computer architecture education","short-title":[],"issued":{"date-parts":[[2003]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1145\/1275521.1275540","relation":{},"subject":[],"published":{"date-parts":[[2003]]}}}