{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T00:06:32Z","timestamp":1772150792080,"version":"3.50.1"},"reference-count":12,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2007,7,1]],"date-time":"2007-07-01T00:00:00Z","timestamp":1183248000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2007,7]]},"abstract":"<jats:p>Flash memory is being rapidly deployed as data storage for mobile devices such as PDAs, MP3 players, mobile phones, and digital cameras, mainly because of its low electronic power, nonvolatile storage, high performance, physical stability, and portability. One disadvantage of flash memory is that prewritten data cannot be dynamically overwritten. Before overwriting prewritten data, a time-consuming erase operation on the used blocks must precede, which significantly degrades the overall write performance of flash memory. In order to solve this \u201cerase-before-write\u201d problem, the flash memory controller can be integrated with a software module, called \u201cflash translation layer (FTL).\u201d Among many FTL schemes available, the log block buffer scheme is considered to be optimum. With this scheme, a small number of log blocks, a kind of write buffer, can improve the performance of write operations by reducing the number of erase operations. However, this scheme can suffer from low space utilization of log blocks. In this paper, we show that there is much room for performance improvement in the log buffer block scheme, and propose an enhanced log block buffer scheme, called FAST (full associative sector translation). Our FAST scheme improves the space utilization of log blocks using fully-associative sector translations for the log block sectors. We also show empirically that our FAST scheme outperforms the pure log block buffer scheme.<\/jats:p>","DOI":"10.1145\/1275986.1275990","type":"journal-article","created":{"date-parts":[[2007,9,14]],"date-time":"2007-09-14T13:44:55Z","timestamp":1189777495000},"page":"18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":530,"title":["A log buffer-based flash translation layer using fully-associative sector translation"],"prefix":"10.1145","volume":"6","author":[{"given":"Sang-Won","family":"Lee","sequence":"first","affiliation":[{"name":"Sungkyunkwan University, Suwon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dong-Joo","family":"Park","sequence":"additional","affiliation":[{"name":"Soongsil University, Seoul, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tae-Sun","family":"Chung","sequence":"additional","affiliation":[{"name":"Ajou University, Suwon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dong-Ho","family":"Lee","sequence":"additional","affiliation":[{"name":"Hanyang University, Ansan, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sangwon","family":"Park","sequence":"additional","affiliation":[{"name":"Hankook University of Foreign Studies, Yongin, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ha-Joo","family":"Song","sequence":"additional","affiliation":[{"name":"Pukyong National University, Busan, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,7]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Ban A. 1995. Flash file system. United States Patent No. 5 404 485 April.  Ban A. 1995. Flash file system. United States Patent No. 5 404 485 April."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/11802167_41"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the 1st Symposium on Operation Systems Design and Implementation (OSDI)","author":"Douglis F.","year":"1994","unstructured":"Douglis , F. , Caceres , R. , Kaashoek , M. F. , Li , K. , Marsh , B. , and Tauber , J. A . 1994. Storage alternatives for mobile computers . In Proceedings of the 1st Symposium on Operation Systems Design and Implementation (OSDI) , Monterey, CA , November 1994 , J. Lepreau, Eds. Usenix Association, Berkeley, CA. 25--37. Douglis, F., Caceres, R., Kaashoek, M. F., Li, K., Marsh, B., and Tauber, J. A. 1994. Storage alternatives for mobile computers. In Proceedings of the 1st Symposium on Operation Systems Design and Implementation (OSDI), Monterey, CA, November 1994, J. Lepreau, Eds. Usenix Association, Berkeley, CA. 25--37."},{"key":"e_1_2_1_4_1","unstructured":"Estakhri P. and Iman B. 1999. Moving sequential sectors within a block of information in a flash memory mass storage architecture United States Patent No. 5 930 815 July.  Estakhri P. and Iman B. 1999. Moving sequential sectors within a block of information in a flash memory mass storage architecture United States Patent No. 5 930 815 July."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1089733.1089735"},{"key":"e_1_2_1_6_1","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy J. L.","year":"2003","unstructured":"Hennessy , J. L. and Patterson , D. A . 2003 . Computer Architecture: A Quantitative Approach , 3 rd ed. Morgan Kaufmann , San Mateo, CA . Hennessy, J. L. and Patterson, D. A. 2003. Computer Architecture: A Quantitative Approach, 3rd ed. Morgan Kaufmann, San Mateo, CA.","edition":"3"},{"key":"e_1_2_1_7_1","unstructured":"Kim B. S. and Lee G. Y. 2002. Method of driving remapping in flash memory and flash memory architecture suitable therefore United States Patent No. 6 381 176 April.  Kim B. S. and Lee G. Y. 2002. Method of driving remapping in flash memory and flash memory architecture suitable therefore United States Patent No. 6 381 176 April."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2002.1010143"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2006.22"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.172"},{"key":"e_1_2_1_11_1","unstructured":"Samsung Electronics. 2005. Nand flash memory & smartmedia data book.  Samsung Electronics. 2005. Nand flash memory & smartmedia data book."},{"key":"e_1_2_1_12_1","unstructured":"Shinohara T. 1999. Flash memory card with block memory address arrangement. United States Patent No. 5 905 993 May.  Shinohara T. 1999. Flash memory card with block memory address arrangement. United States Patent No. 5 905 993 May."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1275986.1275990","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1275986.1275990","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:58:00Z","timestamp":1750258680000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1275986.1275990"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,7]]},"references-count":12,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2007,7]]}},"alternative-id":["10.1145\/1275986.1275990"],"URL":"https:\/\/doi.org\/10.1145\/1275986.1275990","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,7]]},"assertion":[{"value":"2007-07-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}