{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:17Z","timestamp":1750307897261,"version":"3.41.0"},"reference-count":35,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2007,9,1]],"date-time":"2007-09-01T00:00:00Z","timestamp":1188604800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2007,9]]},"abstract":"<jats:p>\n            Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies due to the continuing size reductions and increasing speeds of transistors. Recent studies have attempted to reduce leakage power using integrated architecture and compiler power-gating mechanisms. This approach involves compilers inserting instructions into programs to shut down and wake up components, as appropriate. While early studies showed this approach to be effective, there are concerns about the large amount of power-control instructions being added to programs due to the increasing amount of components equipped with power-gating controls in SoC design platforms. In this article we present a\n            <jats:italic>sink-n-hoist<\/jats:italic>\n            framework for a compiler to generate balanced scheduling of power-gating instructions. Our solution attempts to merge several power-gating instructions into a single compound instruction, thereby reducing the amount of power-gating instructions issued. We performed experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumption using Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further reducing leakage power compared to previous methods.\n          <\/jats:p>","DOI":"10.1145\/1278349.1278364","type":"journal-article","created":{"date-parts":[[2007,10,14]],"date-time":"2007-10-14T12:41:11Z","timestamp":1192365671000},"page":"51","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":18,"title":["Compilation for compact power-gating controls"],"prefix":"10.1145","volume":"12","author":[{"given":"Yi-Ping","family":"You","sequence":"first","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Wen","family":"Huang","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jenq Kuen","family":"Lee","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.845897"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360148"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.126534"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217502"},{"key":"e_1_2_1_6_1","unstructured":"Compaq Computer Corp. 1999. Alpha 21264 Microprocessor Hardware Reference Manual.  Compaq Computer Corp. 1999. Alpha 21264 Microprocessor Hardware Reference Manual."},{"key":"e_1_2_1_7_1","first-page":"2","article-title":"Transistor elements for 30 nm physical gate lengths and beyond","volume":"6","author":"Doyle B.","year":"2002","journal-title":"Intel Technol. J."},{"volume-title":"Proceedings of the 35th International Symposium on Microarchitecture (MICRO)","author":"Dropsho S.","key":"e_1_2_1_8_1"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0377-2217(02)00404-6"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.848473"},{"volume-title":"Proceedings of the IEEE Symposium on Low Power Electronics","author":"Horowitz M.","key":"e_1_2_1_11_1"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"volume-title":"Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT)","author":"Ip H.","key":"e_1_2_1_13_1"},{"key":"e_1_2_1_14_1","unstructured":"Jones R. 2004. Modeling and design techniques reduce 90 nm power. EE Times. http:\/\/www.eetimes.com\/showArticle.jhtml?articleID=26806450.  Jones R. 2004. Modeling and design techniques reduce 90 nm power. EE Times. http:\/\/www.eetimes.com\/showArticle.jhtml?articleID=26806450."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.848210"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774602"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250885"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-6377(98)00043-1"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/762488.762494"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.555992"},{"volume-title":"Proceedings of the 11th International Conference on Compiler Construction (CC)","author":"Rele S.","key":"e_1_2_1_21_1"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design","author":"Roy K.","key":"e_1_2_1_22_1"},{"key":"e_1_2_1_23_1","unstructured":"Semiconductor Industry Assoc. 2004. International technology roadmap for semiconductors.  Semiconductor Industry Assoc. 2004. International technology roadmap for semiconductors."},{"key":"e_1_2_1_24_1","unstructured":"Smith M. D. 1998. The SUIF Machine Library. Division of of Engineering and Applied Science Harvard University.  Smith M. D. 1998. The SUIF Machine Library. Division of of Engineering and Applied Science Harvard University."},{"key":"e_1_2_1_25_1","unstructured":"Stanford Compiler Group. 1995. The SUIF Library. Stanford Compiler Group Stanford University.  Stanford Compiler Group. 1995. The SUIF Library. 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