{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:39Z","timestamp":1750307919801,"version":"3.41.0"},"reference-count":4,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGBED Rev."],"published-print":{"date-parts":[[2006,1]]},"abstract":"<jats:p>The objective of this paper is to enable easy, tight, and safe timing analysis of contemporary complex processors. We exploit the fact that out-of-order processors can be analyzed via simulation in the absence of variable control-flow. In our first technique, Non-Uniform Program Analysis (NUPA), program segments with a single flow of control are analyzed on a complex pipeline via simulation and segments with multiple flows of control are analyzed on a simple pipeline via conventional static analysis. A reconfigurable pipeline with dual complex\/simple modes mirrors the hybrid analysis. Our second technique, Repeatable Execution Constraints for out-of-ORDER (RECORDER), defines constraints that guarantee a single input-independent execution time on an out-of-order pipeline for program segments with multiple flows of control. Thus, execution time can be derived via simulation with arbitrary inputs.<\/jats:p>","DOI":"10.1145\/1279711.1279716","type":"journal-article","created":{"date-parts":[[2007,9,14]],"date-time":"2007-09-14T13:44:55Z","timestamp":1189777495000},"page":"17-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Non-uniform program analysis &amp; repeatable execution constraints"],"prefix":"10.1145","volume":"3","author":[{"given":"Aravindh","family":"Anantaraman","sequence":"first","affiliation":[{"name":"Dept. of ECE, North Carolina State University, Raleigh, NC"}]},{"given":"Eric","family":"Rotenberg","sequence":"additional","affiliation":[{"name":"Dept. of ECE, North Carolina State University, Raleigh, NC"}]}],"member":"320","published-online":{"date-parts":[[2006,1]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859659"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/266388.266562"},{"key":"e_1_2_1_3_1","volume-title":"Proc. 7th Int. Workshop on Object-Oriented Real-Time Dependable Systems","author":"Puschner P.","year":"2002","unstructured":"[ 3 ] P. Puschner , A. Burns . \"Writing Temporally Predictable Code\". Proc. 7th Int. Workshop on Object-Oriented Real-Time Dependable Systems , 2002 . [3] P. Puschner, A. Burns. \"Writing Temporally Predictable Code\". Proc. 7th Int. Workshop on Object-Oriented Real-Time Dependable Systems, 2002."},{"key":"e_1_2_1_4_1","volume-title":"Proc. Int. Sym. on Code Generation and Optimization","author":"Chuang W.","year":"2003","unstructured":"[ 4 ] W. Chuang , B. Calder , J. Ferrante . \"Phi-Predication for Light-Weight If-Conversion\" , Proc. Int. Sym. on Code Generation and Optimization , 2003 . [4] W. Chuang, B. Calder, J. Ferrante. \"Phi-Predication for Light-Weight If-Conversion\", Proc. Int. Sym. on Code Generation and Optimization, 2003."}],"container-title":["ACM SIGBED Review"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1279711.1279716","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1279711.1279716","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:51:33Z","timestamp":1750258293000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1279711.1279716"}},"subtitle":["exploiting out-of-order processors in real-time systems"],"short-title":[],"issued":{"date-parts":[[2006,1]]},"references-count":4,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2006,1]]}},"alternative-id":["10.1145\/1279711.1279716"],"URL":"https:\/\/doi.org\/10.1145\/1279711.1279716","relation":{},"ISSN":["1551-3688"],"issn-type":[{"type":"electronic","value":"1551-3688"}],"subject":[],"published":{"date-parts":[[2006,1]]},"assertion":[{"value":"2006-01-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}