{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:40:24Z","timestamp":1750308024394,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,9,3]],"date-time":"2007-09-03T00:00:00Z","timestamp":1188777600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,9,3]]},"DOI":"10.1145\/1284480.1284522","type":"proceedings-article","created":{"date-parts":[[2012,10,11]],"date-time":"2012-10-11T15:35:23Z","timestamp":1349969723000},"page":"137-141","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Design of a digital FM demodulator based on a 2nd\u00b0 order all-digital phase-locked loop"],"prefix":"10.1145","author":[{"given":"Juan Pablo Martinez","family":"Brito","sequence":"first","affiliation":[{"name":"Federal University of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"}]},{"given":"Sergio","family":"Bampi","sequence":"additional","affiliation":[{"name":"Federal University of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil"}]}],"member":"320","published-online":{"date-parts":[[2007,9,3]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/35.393001"},{"volume-title":"Jentz, B Synthesizing FPGA Cores for Software Defined Radio General Dynamics Decision Systems. 2003 Software Defined Radio Technical Conference and Product Exposition","author":"Huie","key":"e_1_3_2_1_2_1","unstructured":"Huie , J; D'Antonio, P; Pelt , R; Jentz, B Synthesizing FPGA Cores for Software Defined Radio General Dynamics Decision Systems. 2003 Software Defined Radio Technical Conference and Product Exposition November 17-19, 2003-Orlando, Florida. Huie, J; D'Antonio, P; Pelt, R; Jentz, B Synthesizing FPGA Cores for Software Defined Radio General Dynamics Decision Systems. 2003 Software Defined Radio Technical Conference and Product Exposition November 17-19, 2003-Orlando, Florida."},{"key":"e_1_3_2_1_3_1","first-page":"334","volume-title":"Fourth European Conference on, Vol., Iss.","author":"de Fermin R.","year":"1993","unstructured":"de Fermin , R. ; Perez , D. ; Reguero , F. The use of VHDL for the whole design flow of digital radio devices Radio Relay Systems, 1993 ., Fourth European Conference on, Vol., Iss. , 11-14 Oct 1993 Pages: 334 -- 337 . de Fermin, R.; Perez, D.; Reguero, F. The use of VHDL for the whole design flow of digital radio devices Radio Relay Systems, 1993., Fourth European Conference on, Vol., Iss., 11-14 Oct 1993 Pages:334--337."},{"key":"e_1_3_2_1_4_1","first-page":"90","volume-title":"IVC\/VIUF. Proceedings., 1998","author":"McCloskey J.","year":"1998","unstructured":"McCloskey , J. Application of VHDL to software radio technology Verilog HDL Conference and VHDL International Users Forum, 1998 . IVC\/VIUF. Proceedings., 1998 International, Vol., Iss. , 16-19 Mar 1998 Pages: 90 -- 95 . McCloskey, J. Application of VHDL to software radio technology Verilog HDL Conference and VHDL International Users Forum, 1998. IVC\/VIUF. Proceedings., 1998 International, Vol., Iss., 16-19 Mar 1998 Pages:90--95."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2001.941058"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052867"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/30.156724"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1996.488712"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1990.110149"},{"key":"e_1_3_2_1_10_1","first-page":"32","article-title":"Digital signal processing type stereo FM receiver","author":"Hagiwara M.","year":"1986","unstructured":"M. Hagiwara and M. Nakagawa , Digital signal processing type stereo FM receiver , IEEE Trans. Consumer Electron. , vol. C E- 32 , pp. 37--43, Feb. 1986 . M. Hagiwara and M. Nakagawa, Digital signal processing type stereo FM receiver, IEEE Trans. Consumer Electron., vol. CE-32, pp. 37--43, Feb. 1986.","journal-title":"IEEE Trans. Consumer Electron."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/30.125075"},{"key":"e_1_3_2_1_12_1","volume-title":"Solid-State Circuits Conference, 2004","author":"Staszewski R.B.","year":"2004","unstructured":"Staszewski , R.B. ; Chih-Ming Hung ; Maggio, K.; Wallberg , J. ; Leipold , D. ; Balsara , P.T. , All -digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13\/spl mu\/m CMOS , Solid-State Circuits Conference, 2004 . Digest of Technical Papers. ISSCC. 2004 IEEE International Volume , Issue , 15-19 Feb. 2004 Page(s): 272--527 Staszewski, R.B.; Chih-Ming Hung; Maggio, K.; Wallberg, J.; Leipold, D.; Balsara, P.T., All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13\/spl mu\/m CMOS, Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International Volume , Issue , 15-19 Feb. 2004 Page(s): 272--527"},{"issue":"12","key":"e_1_3_2_1_13_1","first-page":"2469","article-title":"All-digital PLL and transmitter for mobile phones Solid-State Circuits","volume":"40","author":"Staszewski","year":"2005","unstructured":"Staszewski , et al. All-digital PLL and transmitter for mobile phones Solid-State Circuits , IEEE Journal of , Vol. 40 , Iss. 12 , Dec. 2005 Pages: 2469 -- 2482 Staszewski, et al. All-digital PLL and transmitter for mobile phones Solid-State Circuits, IEEE Journal of, Vol.40, Iss.12, Dec. 2005 Pages: 2469--2482","journal-title":"IEEE Journal of"},{"issue":"8","key":"e_1_3_2_1_14_1","first-page":"1772","article-title":"The First Fully Integrated Quad-Band GSM\/GPRS Receiver in a 90-nm Digital CMOS Process Solid-State Circuits","volume":"41","author":"Muhammad","year":"2006","unstructured":"Muhammad , et al. The First Fully Integrated Quad-Band GSM\/GPRS Receiver in a 90-nm Digital CMOS Process Solid-State Circuits , IEEE Journal of , Vol. 41 , Iss. 8 , Aug. 2006 Pages: 1772 -- 1783 . Muhammad, et al. The First Fully Integrated Quad-Band GSM\/GPRS Receiver in a 90-nm Digital CMOS Process Solid-State Circuits, IEEE Journal of, Vol.41, Iss.8, Aug. 2006 Pages: 1772-- 1783.","journal-title":"IEEE Journal of"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807398"},{"issue":"8","key":"e_1_3_2_1_16_1","first-page":"1063","article-title":"An ADPLL-based Clock Recovery Circuit, Solid-State Circuits","volume":"34","author":"Hsu B.J.","year":"1999","unstructured":"T.Y. Hsu , B.J. Shieh , and C.Y. Lee , An ADPLL-based Clock Recovery Circuit, Solid-State Circuits , IEEE Journal of Volume 34 , Issue 8 , Aug 1999 Page(s): 1063 -- 1073 . T.Y. Hsu, B.J. Shieh, and C.Y. Lee, An ADPLL-based Clock Recovery Circuit, Solid-State Circuits, IEEE Journal of Volume 34, Issue 8, Aug 1999 Page(s):1063--1073.","journal-title":"IEEE Journal of"},{"key":"e_1_3_2_1_17_1","first-page":"22","article-title":"A Second-Order All-Digital Phase-Locked Loop Communications","author":"Holmes J.","year":"1988","unstructured":"Holmes , J. ; Tegnelia , C . A Second-Order All-Digital Phase-Locked Loop Communications , IEEE Transactions on {legacy, pre- 1988 }, Vol. 22 , Iss.1, Jan 1974 Pages: 62--68. Holmes, J.; Tegnelia, C. A Second-Order All-Digital Phase-Locked Loop Communications, IEEE Transactions on {legacy, pre-1988}, Vol.22, Iss.1, Jan 1974 Pages: 62--68.","journal-title":"IEEE Transactions on {legacy, pre-"},{"key":"e_1_3_2_1_18_1","first-page":"2207","volume-title":"Bell Syst. Tech. J .","author":"Pasternack R. L.","year":"1968","unstructured":"G. Pasternack and R. L. Whalin , Analysis and synthesis of a digital phase-locked loop for FM demodulation , Bell Syst. Tech. J . vol. 47 , pp. 2207 -- 2237 , Dec 1968 . G. Pasternack and R. L. Whalin, Analysis and synthesis of a digital phase-locked loop for FM demodulation, Bell Syst. Tech. J . vol. 47, pp. 2207--2237, Dec 1968."},{"key":"e_1_3_2_1_19_1","first-page":"20","article-title":"The Digital Phase-Locked Loop as a Near-Optimum FM Demodulator Communications","author":"Kelly C.","year":"1988","unstructured":"Kelly , C. ; Gupta , S . The Digital Phase-Locked Loop as a Near-Optimum FM Demodulator Communications , IEEE Transactions on {legacy, pre- 1988 }, Vol. 20 , Iss.3, Jun 1972. Pages: 406--411. Kelly, C.; Gupta, S. The Digital Phase-Locked Loop as a Near-Optimum FM Demodulator Communications, IEEE Transactions on {legacy, pre-1988}, Vol.20, Iss.3, Jun 1972. Pages: 406--411.","journal-title":"IEEE Transactions on {legacy, pre-"},{"key":"e_1_3_2_1_20_1","volume-title":"Phase-Locked Loops Design, Simulation, and Applications, 5\u00b0 Edition","author":"Best R. E.","year":"2003","unstructured":"Best R. E. , Phase-Locked Loops Design, Simulation, and Applications, 5\u00b0 Edition , McGraw-Hill , 2003 . Best R. E., Phase-Locked Loops Design, Simulation, and Applications, 5\u00b0 Edition, McGraw-Hill, 2003."},{"key":"e_1_3_2_1_21_1","volume-title":"Phase-Locked Loops for Wireless Communications Digital, Analog and Optical Implementations, 2\u00b0 Edition","author":"Stephens D. R.","year":"1998","unstructured":"Stephens D. R. Phase-Locked Loops for Wireless Communications Digital, Analog and Optical Implementations, 2\u00b0 Edition , Kluwer Academic Publishers , 1998 . Stephens D. R. Phase-Locked Loops for Wireless Communications Digital, Analog and Optical Implementations, 2\u00b0 Edition, Kluwer Academic Publishers, 1998."},{"key":"e_1_3_2_1_22_1","volume-title":"Modern Control Engineering","author":"Katsuhiko Ogata","year":"2002","unstructured":"Katsuhiko Ogata , Modern Control Engineering , Prentice Hall , 2002 . Katsuhiko Ogata, Modern Control Engineering, Prentice Hall, 2002."},{"key":"e_1_3_2_1_23_1","volume-title":"Digital Signal Processing","author":"John G.","year":"1996","unstructured":"John G. Proakis , Dimitri G. Manolakis , Digital Signal Processing , Prentice Hall , 1996 . John G. Proakis, Dimitri G. Manolakis, Digital Signal Processing, Prentice Hall, 1996."},{"key":"e_1_3_2_1_24_1","volume-title":"Linear Systems","author":"Naresh K.","year":"1991","unstructured":"Naresh K. Sinha , Linear Systems , John Wiley and Sons . Inc, 1991 . Naresh K. Sinha, Linear Systems, John Wiley and Sons. Inc, 1991."}],"event":{"name":"SBCCI07: 20th Symposium on Integrated Circuits and System Design","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Copacabana Rio de Janeiro","acronym":"SBCCI07"},"container-title":["Proceedings of the 20th annual conference on Integrated circuits and systems design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1284480.1284522","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1284480.1284522","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T15:13:55Z","timestamp":1750259635000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1284480.1284522"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,9,3]]},"references-count":24,"alternative-id":["10.1145\/1284480.1284522","10.1145\/1284480"],"URL":"https:\/\/doi.org\/10.1145\/1284480.1284522","relation":{},"subject":[],"published":{"date-parts":[[2007,9,3]]},"assertion":[{"value":"2007-09-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}