{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:39:28Z","timestamp":1750307968018,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,9,3]],"date-time":"2007-09-03T00:00:00Z","timestamp":1188777600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,9,3]]},"DOI":"10.1145\/1284480.1284571","type":"proceedings-article","created":{"date-parts":[[2012,10,11]],"date-time":"2012-10-11T15:35:23Z","timestamp":1349969723000},"page":"348-353","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A software-based methodology for the generation of peripheral test sets based on high-level descriptions"],"prefix":"10.1145","author":[{"given":"Leticia M. V.","family":"Bolzani","sequence":"first","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}]},{"given":"Edgar E.","family":"Sanchez","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}]},{"given":"Matteo Sonza","family":"Reorda","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}]}],"member":"320","published-online":{"date-parts":[[2007,9,3]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Fault-Tolerant Computer System Design","author":"Pradhan D.K.","year":"1996","unstructured":"D.K. Pradhan , Fault-Tolerant Computer System Design , Prentice Hall , 1996 . D.K. Pradhan, Fault-Tolerant Computer System Design, Prentice Hall, 1996."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2005.1568818"},{"key":"e_1_3_2_1_3_1","volume-title":"HLDVT2000: IEEE International High Level Design Validation and Test Workshop","author":"Corno F.","year":"2000","unstructured":"F. Corno , G. Cumani , M. Sonza Reorda , G. Squillero , \" An RT-lev el Fault Model with High Gate Level Correlation\" , HLDVT2000: IEEE International High Level Design Validation and Test Workshop , 2000 F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero, \"An RT-level Fault Model with High Gate Level Correlation\", HLDVT2000: IEEE International High Level Design Validation and Test Workshop, 2000"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-005-0005-7"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675602"},{"key":"e_1_3_2_1_6_1","volume-title":"IEEE International Test Conference","author":"Corno F.","year":"1997","unstructured":"F. Corno , P. Prinetto , M. Sonza Reorda , \" Testability Analysis and ATPG on behaviour RT-level VHDL\", ITC97 , IEEE International Test Conference , 1997 F. Corno, P. Prinetto, M. Sonza Reorda, \"Testability Analysis and ATPG on behaviour RT-level VHDL\", ITC97, IEEE International Test Conference, 1997"},{"key":"e_1_3_2_1_7_1","volume-title":"Proceedings IEEE\/ACM International Conference on Computer Aided Design","author":"Devadas S.","year":"1996","unstructured":"S. Devadas , A. Ghosh , K. Keutzer , \" An Observability-Based Code Coverage Metric for Functional Simulation\" , Proceedings IEEE\/ACM International Conference on Computer Aided Design , 1996 S. Devadas, A. Ghosh, K. Keutzer, \"An Observability-Based Code Coverage Metric for Functional Simulation\", Proceedings IEEE\/ACM International Conference on Computer Aided Design, 1996"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277078"},{"key":"e_1_3_2_1_9_1","unstructured":"http:\/\/www.opencores.org http:\/\/www.opencores.org"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217597"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.310004"},{"key":"e_1_3_2_1_12_1","first-page":"209","volume-title":"Automation &amp","author":"Corno F.","year":"2001","unstructured":"F. Corno , M. Sonza Reorda , G. Squillero , M. Violante , \" On the Test of Microprocessor IP Cores\" , IEEE Design , Automation &amp ; Test in Europe , pp 209 -- 213 , 2001 F. Corno, M. Sonza Reorda, G. Squillero, M. Violante, \"On the Test of Microprocessor IP Cores\", IEEE Design, Automation & Test in Europe, pp 209--213, 2001"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"crossref","first-page":"217","DOI":"10.1109\/ISCAS.2000.858727","volume-title":"ISCAS2000: The 2000 IEEE International Symposium on Circuits and Systems","author":"Chien-Nan Jimmy Liu","year":"2000","unstructured":"Jimmy Liu Chien-Nan , Chang Chen-Yi , Jou Jing-Yang , Lai Ming-Chih , Juan Hsing-Ming , \"A novel approach for functional coverage measurement in HDL Circuits and Systems \", ISCAS2000: The 2000 IEEE International Symposium on Circuits and Systems , pp 217 -- 220 , 2000 Jimmy Liu Chien-Nan, Chang Chen-Yi, Jou Jing-Yang, Lai Ming-Chih, Juan Hsing-Ming, \"A novel approach for functional coverage measurement in HDL Circuits and Systems\", ISCAS2000: The 2000 IEEE International Symposium on Circuits and Systems, pp 217--220, 2000"},{"key":"e_1_3_2_1_14_1","first-page":"83","volume-title":"M. Sonza Reorda, M. Violante, Z. Peng","author":"Sanchez E.","year":"2004","unstructured":"E. Sanchez , M. Sonza Reorda and G. Squillero , \" Test Program Generation From High-level Microprocessor Descriptions\", Test and validation of hardware\/software systems starting from system-level descriptions , Ed. M. Sonza Reorda, M. Violante, Z. Peng , Springer publisher, 179 p, ISBN: 1-85233-899-7, pp. 83 -- 106 , Dec. 2004 E. Sanchez, M. Sonza Reorda and G. Squillero, \"Test Program Generation From High-level Microprocessor Descriptions\", Test and validation of hardware\/software systems starting from system-level descriptions, Ed. M. Sonza Reorda, M. Violante, Z. Peng, Springer publisher, 179 p, ISBN: 1-85233-899-7, pp. 83--106, Dec. 2004"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.68"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2005.38"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2006.19"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/846240.850205"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2007.14"}],"event":{"name":"SBCCI07: 20th Symposium on Integrated Circuits and System Design","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Copacabana Rio de Janeiro","acronym":"SBCCI07"},"container-title":["Proceedings of the 20th annual conference on Integrated circuits and systems design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1284480.1284571","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1284480.1284571","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:58:15Z","timestamp":1750258695000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1284480.1284571"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,9,3]]},"references-count":19,"alternative-id":["10.1145\/1284480.1284571","10.1145\/1284480"],"URL":"https:\/\/doi.org\/10.1145\/1284480.1284571","relation":{},"subject":[],"published":{"date-parts":[[2007,9,3]]},"assertion":[{"value":"2007-09-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}