{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:56:31Z","timestamp":1750308991708,"version":"3.41.0"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2007,6,1]],"date-time":"2007-06-01T00:00:00Z","timestamp":1180656000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,6]]},"abstract":"<jats:p>Hardware accelerators, used as application-specific extensions to the computational capabilities of a system, are efficient mechanisms to enhance the performance and reduce the power dissipation in a System On Chip (SoC). These accelerators execute on the computationally critical part of the application, and offload computations from the scalar processors. In this paper, we present a design automation tool that generates accelerators based on a given application kernel. The accelerators are processing streaming data, and support a programming model which can naturally express a large number of embedded applications, and which results in efficient and fast hardware implementations. We demonstrate the applicability of the tool for architectural space exploration for a number of media applications, with results on area, throughput, and clock speeds.<\/jats:p>","DOI":"10.1145\/1294313.1294318","type":"journal-article","created":{"date-parts":[[2007,10,12]],"date-time":"2007-10-12T15:47:29Z","timestamp":1192204049000},"page":"2-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Mapping streaming architectures on reconfigurable platforms"],"prefix":"10.1145","volume":"35","author":[{"given":"Nikolaos","family":"Bellas","sequence":"first","affiliation":[{"name":"Embedded Systems Research, Motorola Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sek M.","family":"Chai","sequence":"additional","affiliation":[{"name":"Embedded Systems Research, Motorola Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Malcolm","family":"Dwyer","sequence":"additional","affiliation":[{"name":"Embedded Systems Research, Motorola Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dan","family":"Linzmeier","sequence":"additional","affiliation":[{"name":"Embedded Systems Research, Motorola Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,6]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Amarasinghe S. Thies B. Architectures Languages and Compilers for the Streaming Domain. Tutorial at the 12th Annual International Conference on Parallel Architectures and Compilation Techniques New Orleans LA  Amarasinghe S. Thies B. Architectures Languages and Compilers for the Streaming Domain. Tutorial at the 12th Annual International Conference on Parallel Architectures and Compilation Techniques New Orleans LA"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/795658.795878"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/795659.795917"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.839323"},{"key":"e_1_2_1_5_1","volume-title":"University of California","author":"Caspi E.","year":"2000","unstructured":"Caspi E. , Huang R. , Yeh J. , Markovskiy Y. , DeHon A. , Wawrzynek J. Stream Computations organized for Reconfigurable Execution (SCORE): Introduction and Tutorial. BRASS research group technical report , University of California , Berkeley , August 2000 Caspi E., Huang R., Yeh J., Markovskiy Y., DeHon A., Wawrzynek J. Stream Computations organized for Reconfigurable Execution (SCORE): Introduction and Tutorial. BRASS research group technical report, University of California, Berkeley, August 2000"},{"key":"e_1_2_1_6_1","first-page":"141","volume-title":"Proceedings of the 36th International Conference on Microarchitecture","author":"Chirisescu S.","year":"2003","unstructured":"Chirisescu S. , et. al. The Reconfigurable Streaming Vector Processor, RSVP#8482; . Proceedings of the 36th International Conference on Microarchitecture , December 2003 , pp. 141 -- 150 , San Diego, CA Chirisescu S., et. al. The Reconfigurable Streaming Vector Processor, RSVP#8482;. Proceedings of the 36th International Conference on Microarchitecture, December 2003, pp. 141--150, San Diego, CA"},{"key":"e_1_2_1_7_1","first-page":"129","volume-title":"Processor Acceleration Through Automated Instruction Set Customization. Proceedings of the 36th International Symposium on Microarchitecture","author":"Clark N.","year":"2003","unstructured":"Clark N. , Zhong H. , and Mahlke S . Processor Acceleration Through Automated Instruction Set Customization. Proceedings of the 36th International Symposium on Microarchitecture , December 3-5, 2003 , pp. 129 -- 140 , San Diego, CA Clark N., Zhong H., and Mahlke S. Processor Acceleration Through Automated Instruction Set Customization. Proceedings of the 36th International Symposium on Microarchitecture, December 3-5, 2003, pp. 129--140, San Diego, CA"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1048935.1050187"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307527"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/549928.795752"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/795659.795916"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2005.7476595"},{"key":"e_1_2_1_15_1","volume-title":"Carter N. P. Clustered Programmable-Reconfigurable Processors. Proceedings of the 1st IEEE International Conference on Field Programmable Technology (FPT)","author":"Gottlieb D. B.","year":"2002","unstructured":"Gottlieb D. B. , Cook J. J. , Walstrom J. D. , Ferrera S , Wang C. W. , Carter N. P. Clustered Programmable-Reconfigurable Processors. Proceedings of the 1st IEEE International Conference on Field Programmable Technology (FPT) , December 2002 . Gottlieb D. B., Cook J. J., Walstrom J. D., Ferrera S, Wang C. W., Carter N. P. Clustered Programmable-Reconfigurable Processors. Proceedings of the 1st IEEE International Conference on Field Programmable Technology (FPT), December 2002."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2005.7476576"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.240075"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2002.1033026"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996811"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/JRA.1987.1087088"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2003.1275757"},{"key":"e_1_2_1_22_1","volume-title":"Practical FPGA Programming in C","author":"Pellerin D.","year":"2005","unstructured":"Pellerin D. , Thibault S. Practical FPGA Programming in C . Prentice Hall , 2005 Pellerin D., Thibault S. Practical FPGA Programming in C. Prentice Hall, 2005"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF03356742"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.920828"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277135"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.898829"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339687"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046216"},{"key":"e_1_2_1_32_1","unstructured":"Celoxica Corporation Handel-C language reference manual www.celoxica.com  Celoxica Corporation Handel-C language reference manual www.celoxica.com"},{"key":"e_1_2_1_33_1","unstructured":"Automated Configurable Processor Design Flow White Paper www.tensilica.com  Automated Configurable Processor Design Flow White Paper www.tensilica.com"},{"key":"e_1_2_1_34_1","unstructured":"Virtex-4 FPGA handbook www.xilinx.com August 2004  Virtex-4 FPGA handbook www.xilinx.com August 2004"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1294313.1294318","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1294313.1294318","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:41:18Z","timestamp":1750282878000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1294313.1294318"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,6]]},"references-count":33,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2007,6]]}},"alternative-id":["10.1145\/1294313.1294318"],"URL":"https:\/\/doi.org\/10.1145\/1294313.1294318","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2007,6]]},"assertion":[{"value":"2007-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}