{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:56:31Z","timestamp":1750308991922,"version":"3.41.0"},"reference-count":21,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2007,6,1]],"date-time":"2007-06-01T00:00:00Z","timestamp":1180656000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,6]]},"abstract":"<jats:p>Embedded systems designers that use FPGAs are increasingly including<jats:italic>soft processors<\/jats:italic>in their designs (configurable processors built in the programmable logic of the FPGA). While there has been a significant amount of research on adding custom instructions and accelerators to soft processors, these are typically used to extend an unmodified base ISA targeted by generic compilation such as with unmodified gcc. In this paper we explore several opportunities for the compiler to optimize the code generated for soft processors through application-specific customization of the base ISA---techniques that are orthogonal to adding custom instructions. In particular we explore: (i) low level software-hardware trade-offs between basic instructions; (ii) the utility of ISA-specific features---in particular for the delay slots and Hi\/Lo registers in the MIPS ISA; and (iii) application specific register management. We find that through these techniques that have no hardware cost we can improve the area efficiency of soft processors by 12% on average across a suite of benchmarks, and by up to 47% in the best case.<\/jats:p>","DOI":"10.1145\/1294313.1294319","type":"journal-article","created":{"date-parts":[[2007,10,12]],"date-time":"2007-10-12T15:47:29Z","timestamp":1192204049000},"page":"9-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Custom code generation for soft processors"],"prefix":"10.1145","volume":"35","author":[{"given":"Martin","family":"Labrecque","sequence":"first","affiliation":[{"name":"University of Toronto"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter","family":"Yiannacouras","sequence":"additional","affiliation":[{"name":"University of Toronto"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. Gregory","family":"Steffan","sequence":"additional","affiliation":[{"name":"University of Toronto"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"crossref","unstructured":"J. Ball \"The Nios II Family of Configurable Soft-Core Processors \" Hot Chips Altera August 2005. J. Ball \"The Nios II Family of Configurable Soft-Core Processors \" Hot Chips Altera August 2005.","DOI":"10.1109\/HOTCHIPS.2005.7476599"},{"key":"e_1_2_1_2_1","unstructured":"Xilinx Inc. \"MicroBlaze RISC 32-Bit Soft Processor \" August 2001. Xilinx Inc. \"MicroBlaze RISC 32-Bit Soft Processor \" August 2001."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1023833.1023844"},{"key":"e_1_2_1_4_1","unstructured":"Altera Corporation \"Nios II C-to-Hardware Acceleration Compiler \" http:\/\/www.altera.com\/c2h. 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Luk \"CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools \" in International Conference on Field Programmable Logic (FPL) August 2005."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.38"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046206"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086325"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117231"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016768"},{"key":"e_1_2_1_11_1","unstructured":"MIPS Technologies Inc. \"The MIPS RISC architecture \" http:\/\/www.mips.com MIPS Technologies. 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Fowler \"MINT: a front end for efficient simulation of shared-memory multiprocessors \" in Proceedings of the Second International Workshop on Modeling Analysis and Simulation of Computer and Telecommunication Systems NC USA January 1994 pp. 201--207. J. Veenstra and R. Fowler \"MINT: a front end for efficient simulation of shared-memory multiprocessors \" in Proceedings of the Second International Workshop on Modeling Analysis and Simulation of Computer and Telecommunication Systems NC USA January 1994 pp. 201--207.","DOI":"10.1109\/MASCOT.1994.284422"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503072"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1294313.1294319","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1294313.1294319","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:41:18Z","timestamp":1750282878000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1294313.1294319"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,6]]},"references-count":21,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2007,6]]}},"alternative-id":["10.1145\/1294313.1294319"],"URL":"https:\/\/doi.org\/10.1145\/1294313.1294319","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2007,6]]},"assertion":[{"value":"2007-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}