{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:56:31Z","timestamp":1750308991946,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2007,6,1]],"date-time":"2007-06-01T00:00:00Z","timestamp":1180656000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,6]]},"abstract":"<jats:p>Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such approaches are prone to a fundamental trade-off between the architectural diversity they can provide and the latency of architectural change, their fixed-configuration performance and the complexity of finding the best architectural configuration for the workload at hand. In this study we argue that the full potential of dynamic architectural customization can only be achieved by diminishing the effect of the degree of available architectural diversity on the aforementioned performance factors.<\/jats:p>\n          <jats:p>The performance of a statically designed processing core in a heterogeneous multi-core system is independent of the architectural diversity available. In addition, it is apparent that concurrent execution of code on differently architected cores automatically reveals which architecture is more suitable for the characteristics of a particular workload.<\/jats:p>\n          <jats:p>We therefore propose architectural contesting; the redundant execution of code on a number of differently architected processors (each customized for a different set of workload characteristics) in a leader follower arrangement, such that the leader and follower cores continuously shift roles as one core or the other becomes more favorable for new code phases. In this manner effective execution is naturally transferred from one static architecture to the other with little latency.<\/jats:p>\n          <jats:p>In this study, we show that the contesting of only processor width can yield an average speedup of 7.5% and up to 12.5% in integer SPEC benchmarks.<\/jats:p>","DOI":"10.1145\/1294313.1294321","type":"journal-article","created":{"date-parts":[[2007,10,12]],"date-time":"2007-10-12T15:47:29Z","timestamp":1192204049000},"page":"28-35","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Architectural\n            <i>contesting<\/i>"],"prefix":"10.1145","volume":"35","author":[{"given":"Hashem H.","family":"Najaf-abadi","sequence":"first","affiliation":[{"name":"North Carolina State University"}]},{"given":"Eric","family":"Rotenberg","sequence":"additional","affiliation":[{"name":"North Carolina State University"}]}],"member":"320","published-online":{"date-parts":[[2007,6]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956569"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.917541"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.51"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545241"},{"key":"e_1_2_1_6_1","volume-title":"4th Workshop on Feedback-Directed and Dynamic Optimization (FDDO4)","author":"Huang M.","year":"2001","unstructured":"M. Huang , J. Renau , and J. Torrellas . \" Profile-based energy reduction for high-performance processors \". In 4th Workshop on Feedback-Directed and Dynamic Optimization (FDDO4) , Dec. 2001 . M. Huang, J. Renau, and J. Torrellas. \"Profile-based energy reduction for high-performance processors\". In 4th Workshop on Feedback-Directed and Dynamic Optimization (FDDO4), Dec. 2001."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859657"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/290940.290988"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279397"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.814321"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379266"},{"key":"e_1_2_1_13_1","first-page":"147","volume-title":"Symp. on High-Perf. Comp. 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Dropsho , \" Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microarchitecture \", IBM Watson Conf. on the Intera. Between Arch., Circuits, and Compilers , pp. 136 -- 143 , Oct. 2004 . L. Chen, D. H. Albonesi, and S. Dropsho, \"Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microarchitecture\", IBM Watson Conf. on the Intera. Between Arch., Circuits, and Compilers, pp. 136--143, Oct. 2004."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152162"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.363382"},{"key":"e_1_2_1_25_1","volume-title":"Kluwer Academic Publishers","author":"Franklin M.","year":"2002","unstructured":"M. Franklin , \"Multiscalar Processors\" , Kluwer Academic Publishers , 2002 . M. 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