{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:40:32Z","timestamp":1750308032112,"version":"3.41.0"},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2007,11,1]],"date-time":"2007-11-01T00:00:00Z","timestamp":1193875200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2007,11]]},"abstract":"<jats:p>Advances in fabrication technology of nanoscale devices such as nanowires, carbon nanotubes and molecular switches provide new opportunities for implementing cluster-based FPGAs. Extensive research is needed to evaluate area and performance of FPGAs made from these devices and compare with their CMOS counterparts. In this work, we propose a hybrid FPGA that uses nanoscale clusters with a functionality similar to the clusters of traditional CMOS FPGAs. The proposed cluster is constructed by a crossbar of nanowires and can be configured to implement the required LUTs and intracluster MUXes. A CMOS interface is also proposed to provide configuration and memory elements for the nanoscale cluster. In the proposed architecture, inter-cluster routing remains at CMOS scale. We have developed models for area and delay of clusters and interconnects of the proposed hybrid FPGA. FPGA tools are configured with these models and used to synthesize and configure the benchmark circuits onto the hybrid FPGAs with NiSi nanowires or nanotubes. Experiments are conducted to evaluate and compare area and performance of the hybrid FPGA and traditional CMOS FPGA (scaled to 22nm). Up to 82% area reduction was obtained from implementing MCNC benchmarks on the hybrid FPGA. Performance of the hybrid FPGA is shown to be close to that of CMOS FPGA.<\/jats:p>","DOI":"10.1145\/1295231.1295236","type":"journal-article","created":{"date-parts":[[2007,11,30]],"date-time":"2007-11-30T14:24:58Z","timestamp":1196432698000},"page":"15","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing"],"prefix":"10.1145","volume":"3","author":[{"given":"Reza M.P.","family":"Rad","sequence":"first","affiliation":[{"name":"University of Maryland, Baltimore County"}]},{"given":"Mohammad","family":"Tehranipoor","sequence":"additional","affiliation":[{"name":"University of Connecticut"}]}],"member":"320","published-online":{"date-parts":[[2007,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep Submicron FPGAs. Norwell MA.   Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep Submicron FPGAs. Norwell MA.","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1559439"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.272.5258.85"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1363692"},{"key":"e_1_2_1_6_1","first-page":"149","article-title":"High performance silicon nanowire field effect transistors. Nano","volume":"3","author":"Cui Y.","year":"2003","unstructured":"Cui , Y. , Zhong , Z. , Wang , D. , Wang , W. U. , and Lieber , C. M. 2003 . High performance silicon nanowire field effect transistors. Nano . Lett. 3 , 2, 149 -- 152 . Cui, Y., Zhong, Z., Wang, D., Wang, W. U., and Lieber, C. M. 2003. High performance silicon nanowire field effect transistors. Nano. Lett. 3, 2, 149--152.","journal-title":"Lett."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084748.1084750"},{"key":"e_1_2_1_8_1","doi-asserted-by":"crossref","unstructured":"Dekker C. 1999. Carbon nanotubes as molecular quantum wires. Phys. Today 22--28.  Dekker C. 1999. Carbon nanotubes as molecular quantum wires. Phys. Today 22--28.","DOI":"10.1063\/1.882658"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065820"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1002\/anie.200300608"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379262"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.1066192"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.291.5504.630"},{"key":"e_1_2_1_14_1","unstructured":"Kuekes P. J. and Williams R. S. 2000. Demultiplexer for a molecular wire crossbar network U.S. Patent No. 6256767.  Kuekes P. J. and Williams R. S. 2000. Demultiplexer for a molecular wire crossbar network U.S. Patent No. 6256767."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl048687z"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl034031e"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.279.5348.208"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.97624"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147094"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117241"},{"key":"e_1_2_1_21_1","unstructured":"Semiconductor Industry Association. 2005. International technology roadmap for semiconductors (ITRS). http:\/\/public.itrs.net\/.  Semiconductor Industry Association. 2005. International technology roadmap for semiconductors (ITRS). http:\/\/public.itrs.net\/."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/15\/8\/003"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/16\/6\/045"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl034268a"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1295231.1295236","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1295231.1295236","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T15:14:08Z","timestamp":1750259648000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1295231.1295236"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,11]]},"references-count":24,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2007,11]]}},"alternative-id":["10.1145\/1295231.1295236"],"URL":"https:\/\/doi.org\/10.1145\/1295231.1295236","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2007,11]]},"assertion":[{"value":"2007-11-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}