{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:27Z","timestamp":1750307787522,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,12,3]],"date-time":"2007-12-03T00:00:00Z","timestamp":1196640000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,12,3]]},"DOI":"10.1145\/1323548.1323561","type":"proceedings-article","created":{"date-parts":[[2007,12,7]],"date-time":"2007-12-07T19:19:41Z","timestamp":1197055181000},"page":"47-56","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture"],"prefix":"10.1145","author":[{"given":"Avinash","family":"Kodi","sequence":"first","affiliation":[{"name":"Ohio University, Athens, OH &amp; University of Arizona, Tucson, AZ"}]},{"given":"Ashwini","family":"Sarathy","sequence":"additional","affiliation":[{"name":"University of Arizona, Tucson, AZ"}]},{"given":"Ahmed","family":"Louri","sequence":"additional","affiliation":[{"name":"University of Arizona, Tucson, AZ"}]}],"member":"320","published-online":{"date-parts":[[2007,12,3]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382601"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.50"},{"key":"e_1_3_2_1_7_1","first-page":"105","volume-title":"USA","author":"Wang H. S.","year":"2003","unstructured":"H. S. Wang , L. S. Peh , and S. Malik , \" Power-driven design of router microarchitectures in on-chip networks,\" in Proceedings of the 36th Annual ACM\/IEEE International Symposium on Microarchitecture (MICRO), Washington DC , USA , pp. 105 -- 116 , December 3-5, 2003 . H. S. Wang, L. S. Peh, and S. Malik, \"Power-driven design of router microarchitectures in on-chip networks,\" in Proceedings of the 36th Annual ACM\/IEEE International Symposium on Microarchitecture (MICRO), Washington DC, USA, pp. 105--116, December 3-5, 2003."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077692"},{"key":"e_1_3_2_1_9_1","unstructured":"\"2006 workshop on on-and off-chip interconnection networks for multicore systems (http:\/\/www.ece.ucdavis.edu\/~ocin06\/program.html) \" December 6-7 2006.  \"2006 workshop on on-and off-chip interconnection networks for multicore systems (http:\/\/www.ece.ucdavis.edu\/~ocin06\/program.html) \" December 6-7 2006."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.6"},{"key":"e_1_3_2_1_11_1","first-page":"188","volume-title":"Low-latency virtual channel routers for on-chip networks,\" in Proceedings of International Symposium on Computer Architecture (ISCA)Munchen,Germany","author":"Mullins R.","year":"2004","unstructured":"R. Mullins , A. West , and S. Moore , \" Low-latency virtual channel routers for on-chip networks,\" in Proceedings of International Symposium on Computer Architecture (ISCA)Munchen,Germany , pp. 188 -- 197 , June 19--23, 2004 . R. Mullins, A. West, and S. Moore, \"Low-latency virtual channel routers for on-chip networks,\" in Proceedings of International Symposium on Computer Architecture (ISCA)Munchen,Germany, pp. 188--197, June 19--23, 2004."},{"key":"e_1_3_2_1_12_1","first-page":"255","volume-title":"Mexico","author":"Peh L. S.","year":"2001","unstructured":"L. S. Peh and W. J. Dally , \" A delay model and speculative architecture for pipelined routers,\" in Proceedings of the 7th International Symposium on High-Performance Computer Architecture (HPCA)Nuevo Leone , Mexico , pp. 255 -- 266 , January , 2001 . L. S. Peh and W. J. Dally, \"A delay model and speculative architecture for pipelined routers,\" in Proceedings of the 7th International Symposium on High-Performance Computer Architecture (HPCA)Nuevo Leone, Mexico, pp. 255--266, January, 2001."},{"key":"e_1_3_2_1_13_1","volume-title":"USA","author":"Dally W. J.","year":"2004","unstructured":"W. J. Dally and B. Towles , Principles and Practices of Interconnection Networks Morgan Kaufmann, San Fransisco , USA , 2004 . W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks Morgan Kaufmann, San Fransisco, USA, 2004."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.804706"},{"key":"e_1_3_2_1_15_1","first-page":"346","article-title":"Elastic interconnects: Repeater-inserted long wiring capable of compressing and decompressing data","author":"Mizuno M.","year":"2001","unstructured":"M. Mizuno , W. J. Dally , and H. Onishi , \" Elastic interconnects: Repeater-inserted long wiring capable of compressing and decompressing data ,\" in Proceedings of the IEEE International Solid-State Circuits Conference San Fransisco, CA ,USA , pp. 346 -- 347 , February 5-7, 2001 . M. Mizuno, W. J. Dally, and H. Onishi, \"Elastic interconnects: Repeater-inserted long wiring capable of compressing and decompressing data,\" in Proceedings of the IEEE International Solid-State Circuits Conference San Fransisco, CA ,USA, pp. 346--347, February 5-7,2001.","journal-title":"Proceedings of the IEEE International Solid-State Circuits Conference San Fransisco, CA ,USA"},{"key":"e_1_3_2_1_16_1","first-page":"466","volume-title":"USA","author":"Ni N.","year":"1998","unstructured":"N. Ni , M. Pirvu , and L. Bhuyan , \" Circular buffered switch design with wormhole routing and virtual channels,\" in Proceedings of the International Conference on Computer Design (ICCD)Austin, TX , USA , pp. 466 -- 473 , October , 1998 . N. Ni, M. Pirvu, and L. Bhuyan, \"Circular buffered switch design with wormhole routing and virtual channels,\" in Proceedings of the International Conference on Computer Design (ICCD)Austin, TX, USA, pp. 466--473, October, 1998."},{"key":"e_1_3_2_1_17_1","first-page":"343","volume-title":"USA","author":"Tamir Y.","year":"1988","unstructured":"Y. Tamir and G. L. Frazier , \" High-performance multiqueue buffers for VLSI communication switches,\" in Proceedings of the 15th Annual International Symposium on Computer Architecture (ISCA)Honolulu, Hawaii , USA , pp. 343 -- 354 , May- June , 1988 . Y. Tamir and G. L. Frazier, \"High-performance multiqueue buffers for VLSI communication switches,\" in Proceedings of the 15th Annual International Symposium on Computer Architecture (ISCA)Honolulu, Hawaii, USA, pp. 343--354, May-June, 1988."},{"key":"e_1_3_2_1_18_1","first-page":"294","volume-title":"Turkey","author":"Wang H. S.","year":"2002","unstructured":"H. S. Wang , X. Zhu , L. S. Peh , and S. Malik , \" Orion: A power-performance simulator for interconnection networks,\" in Proceedings of the 35th Annual ACM\/IEEE International Symposium on Microarchitecture (MICRO) Istanbul , Turkey , pp. 294 -- 305 , November 18-22, 2002 . H. S. Wang, X. Zhu, L. S. Peh, and S. Malik, \"Orion: A power-performance simulator for interconnection networks,\" in Proceedings of the 35th Annual ACM\/IEEE International Symposium on Microarchitecture (MICRO) Istanbul, Turkey, pp. 294--305, November 18-22, 2002."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871531"},{"key":"e_1_3_2_1_20_1","first-page":"320","volume-title":"USA","author":"Zeng A. Y.","year":"2004","unstructured":"A. Y. Zeng , K. Rose , and R. J. Gutmann , \" Cache array architecture optimization at deep submicron technologies,\" in Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors San Jose, CA , USA , pp. 320 -- 325 , October 11-13, 2004 . A. Y. Zeng, K. Rose, and R. J. Gutmann, \"Cache array architecture optimization at deep submicron technologies,\" in Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors San Jose, CA, USA, pp. 320--325, October 11-13, 2004."}],"event":{"name":"ANCS07: Symposium on Architecture for Networking and Communications Systems","sponsor":["SIGCOMM ACM Special Interest Group on Data Communication","ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Orlando Florida USA","acronym":"ANCS07"},"container-title":["Proceedings of the 3rd ACM\/IEEE Symposium on Architecture for networking and communications systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1323548.1323561","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1323548.1323561","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:14Z","timestamp":1750254974000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1323548.1323561"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,12,3]]},"references-count":20,"alternative-id":["10.1145\/1323548.1323561","10.1145\/1323548"],"URL":"https:\/\/doi.org\/10.1145\/1323548.1323561","relation":{},"subject":[],"published":{"date-parts":[[2007,12,3]]},"assertion":[{"value":"2007-12-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}