{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:19:07Z","timestamp":1780355947830,"version":"3.54.1"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2007,12,1]],"date-time":"2007-12-01T00:00:00Z","timestamp":1196467200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2007,12]]},"abstract":"<jats:p>Space-based radar is a suite of applications that presents many unique system design challenges. In this paper, we investigate use of RapidIO, a new high-performance embedded systems interconnect, in addressing issues associated with the high network bandwidth requirements of real-time ground moving target indicator (GMTI), and synthetic aperture Radar (SAR) applications in satellite systems. Using validated simulation, we study several critical issues related to the RapidIO network and algorithms under study. The results show that RapidIO is a promising platform for space-based radar using emerging technology, providing network bandwidth to enable parallel computation previously unattainable in an embedded satellite system.<\/jats:p>","DOI":"10.1145\/1324969.1324970","type":"journal-article","created":{"date-parts":[[2008,1,18]],"date-time":"2008-01-18T18:45:29Z","timestamp":1200681929000},"page":"1-38","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["RapidIO for radar processing in advanced space systems"],"prefix":"10.1145","volume":"7","author":[{"given":"David","family":"Bueno","sequence":"first","affiliation":[{"name":"University of Florida, High-performance Computing and Simulation (HCS) Research Lab, Gainsville, Florida"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chris","family":"Conger","sequence":"additional","affiliation":[{"name":"University of Florida, High-performance Computing and Simulation (HCS) Research Lab, Gainsville, Florida"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alan D.","family":"George","sequence":"additional","affiliation":[{"name":"University of Florida, High-performance Computing and Simulation (HCS) Research Lab, Gainsville, Florida"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ian","family":"Troxel","sequence":"additional","affiliation":[{"name":"University of Florida, High-performance Computing and Simulation (HCS) Research Lab, Gainsville, Florida"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Adam","family":"Leko","sequence":"additional","affiliation":[{"name":"University of Florida, High-performance Computing and Simulation (HCS) Research Lab, Gainsville, Florida"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2007,12,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-rsn:19960790"},{"key":"e_1_2_1_2_1","unstructured":"Bouvier D. 2003. RapidIO: the interconnect architecture for high performance embedded systems. White Paper.  Bouvier D. 2003. RapidIO: the interconnect architecture for high performance embedded systems. White Paper."},{"key":"e_1_2_1_3_1","volume-title":"IEEE National Radar Conference, Syracuse, NY (May). 331--336","author":"Brown R.","unstructured":"Brown , R. and Linderman , R . 1997. Algorithm development for an airborne real-time STAP demonstration . In IEEE National Radar Conference, Syracuse, NY (May). 331--336 . Brown, R. and Linderman, R. 1997. Algorithm development for an airborne real-time STAP demonstration. In IEEE National Radar Conference, Syracuse, NY (May). 331--336."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCN.2004.116"},{"key":"e_1_2_1_5_1","volume-title":"Eighth Annual Workshop on High Performance Embedded Computing, Lexington, MA (Sept.).","author":"Bueno D.","unstructured":"Bueno , D. , Conger , C. , Leko , A. , Troxel , I. , and George , A. D . 2004b. Virtual prototyping and performance analysis of RapdIO-based system architectures for space-based radar . In Eighth Annual Workshop on High Performance Embedded Computing, Lexington, MA (Sept.). Bueno, D., Conger, C., Leko, A., Troxel, I., and George, A. D. 2004b. Virtual prototyping and performance analysis of RapdIO-based system architectures for space-based radar. In Eighth Annual Workshop on High Performance Embedded Computing, Lexington, MA (Sept.)."},{"key":"e_1_2_1_6_1","volume-title":"Ninth Annual Workshop on High Performance Embedded Computing, Lexington, MA (Sept.).","author":"Bueno D.","unstructured":"Bueno , D. , Conger , C. , Leko , A. , Troxel , I. , and George , A. D . 2005. RapidIO-based space system architectures for synthetic aperture radar and ground moving target indicator . In Ninth Annual Workshop on High Performance Embedded Computing, Lexington, MA (Sept.). Bueno, D., Conger, C., Leko, A., Troxel, I., and George, A. D. 2005. RapidIO-based space system architectures for synthetic aperture radar and ground moving target indicator. In Ninth Annual Workshop on High Performance Embedded Computing, Lexington, MA (Sept.)."},{"key":"e_1_2_1_7_1","unstructured":"Choudhary A. Liao W. K. Weiner D. Varshney P. Linderman R. and Linderman M. 1998a. Design implementation and evaluation of parallel pipelined STAP on parallel computers. Technical report Northwestern University.  Choudhary A. Liao W. K. Weiner D. Varshney P. Linderman R. and Linderman M. 1998a. Design implementation and evaluation of parallel pipelined STAP on parallel computers. Technical report Northwestern University."},{"key":"e_1_2_1_8_1","volume-title":"IEEE 12th International Parallel Processing Symposium, Orlando, FL (Mar--Apr.). 220--225","author":"Choudhary A.","unstructured":"Choudhary , A. , Liao , W. K. , Weiner , D. , Varshney , P. , Linderman , R. , Linderman , M. , and Brown , R . 1998a. Design, implementation, and evaluation of parallel pipelined STAP on parallel computers . In IEEE 12th International Parallel Processing Symposium, Orlando, FL (Mar--Apr.). 220--225 . Choudhary, A., Liao, W. K., Weiner, D., Varshney, P., Linderman, R., Linderman, M., and Brown, R. 1998a. Design, implementation, and evaluation of parallel pipelined STAP on parallel computers. In IEEE 12th International Parallel Processing Symposium, Orlando, FL (Mar--Apr.). 220--225."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1953.tb01433.x"},{"key":"e_1_2_1_10_1","volume-title":"RapidIO---the embedded system interconnect","author":"Fuller S.","unstructured":"Fuller , S. 2005. RapidIO---the embedded system interconnect . Wiley , New York . Fuller, S. 2005. RapidIO---the embedded system interconnect. Wiley, New York."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/35.533919"},{"key":"e_1_2_1_12_1","volume-title":"Performance analysis of a space-based GMTI radar system using separated spacecraft interferometry. Master's thesis","author":"Hacker T. L.","unstructured":"Hacker , T. L. 2000. Performance analysis of a space-based GMTI radar system using separated spacecraft interferometry. Master's thesis , Massachusetts Institute of Technology , Cambridge, MA . Hacker, T. L. 2000. Performance analysis of a space-based GMTI radar system using separated spacecraft interferometry. Master's thesis, Massachusetts Institute of Technology, Cambridge, MA."},{"key":"e_1_2_1_13_1","volume-title":"Eighth Annual Workshop on High Performance Embedded Computing, Lexington, MA (Sept.).","author":"Kepner J.","unstructured":"Kepner , J. , Currie , T. , Kim , H. , Matthew , B. , Mccabe , A. , Moore , M. , Rabinkin , D. , Reuther , A. , Rhoades , A. , Tella , L. , and Travinn , N . 2004. Deployment of SAR and GMTI signal processing on a Boeing 707 aircraft using pMatlab and a bladed Linux cluster . In Eighth Annual Workshop on High Performance Embedded Computing, Lexington, MA (Sept.). Kepner, J., Currie, T., Kim, H., Matthew, B., Mccabe, A., Moore, M., Rabinkin, D., Reuther, A., Rhoades, A., Tella, L., and Travinn, N. 2004. Deployment of SAR and GMTI signal processing on a Boeing 707 aircraft using pMatlab and a bladed Linux cluster. In Eighth Annual Workshop on High Performance Embedded Computing, Lexington, MA (Sept.)."},{"key":"e_1_2_1_14_1","volume-title":"2nd International Workshop on Embedded Systems and Applications","author":"Lee M.","unstructured":"Lee , M. and Prasanna , V. K . 1997. High throughput-rate parallel algorithms for space time adaptive processing . In 2nd International Workshop on Embedded Systems and Applications , Geneva, Switzerland (Apr.). Lee, M. and Prasanna, V. K. 1997. High throughput-rate parallel algorithms for space time adaptive processing. In 2nd International Workshop on Embedded Systems and Applications, Geneva, Switzerland (Apr.)."},{"key":"e_1_2_1_15_1","volume-title":"Leopard Logic unveils RapidIO implementation platform based on its Hyperblox embedded FPGA cores","author":"Leopard Logic","unstructured":"Leopard Logic 2002. Leopard Logic unveils RapidIO implementation platform based on its Hyperblox embedded FPGA cores . Press release. Leopard Logic 2002. Leopard Logic unveils RapidIO implementation platform based on its Hyperblox embedded FPGA cores. Press release."},{"key":"e_1_2_1_16_1","volume-title":"IEEE National Radar Conference, Syracuse, NY (May). 54--59","author":"Linderman M.","unstructured":"Linderman , M. and Linderman , R . 1997. Real-time STAP demonstration on an embedded high performance computer . In IEEE National Radar Conference, Syracuse, NY (May). 54--59 . Linderman, M. and Linderman, R. 1997. Real-time STAP demonstration on an embedded high performance computer. In IEEE National Radar Conference, Syracuse, NY (May). 54--59."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/224170.224281"},{"key":"e_1_2_1_18_1","unstructured":"Motorola Semiconductor 2000. RapidIO: An embedded system component network architecture. White Paper.  Motorola Semiconductor 2000. RapidIO: An embedded system component network architecture. White Paper."},{"key":"e_1_2_1_19_1","unstructured":"Nohara T. Weber P. Premji A. and Livingstone C. 2000. SAR-GMTI processing with Canada's Radarsat 2 satellite. In IEEE Adaptive Systems for Signal Processing Communications and Control Symposium Lake Louise Canada (Oct.). 376--384.  Nohara T. Weber P. Premji A. and Livingstone C. 2000. SAR-GMTI processing with Canada's Radarsat 2 satellite. In IEEE Adaptive Systems for Signal Processing Communications and Control Symposium Lake Louise Canada (Oct.). 376--384."},{"key":"e_1_2_1_20_1","volume-title":"High Performance Mass Storage and Parallel I\/O: Technologies and Applications","author":"Pfeister G. F.","unstructured":"Pfeister , G. F. 2001. An introduction to the InfiniBand architecture . In High Performance Mass Storage and Parallel I\/O: Technologies and Applications , H. Jin, T. Cortes, and R. Buyya, Eds. IEEE\/Wiley Press , New York . 617--632. Pfeister, G. F. 2001. An introduction to the InfiniBand architecture. In High Performance Mass Storage and Parallel I\/O: Technologies and Applications, H. Jin, T. Cortes, and R. Buyya, Eds. IEEE\/Wiley Press, New York. 617--632."},{"key":"e_1_2_1_21_1","volume-title":"RapidIO technical deep dive 2: parallel and serial PHY. Motorola Smart Networks Developer Forum","author":"Porter J.","year":"2003","unstructured":"Porter , J. 2003. RapidIO technical deep dive 2: parallel and serial PHY. Motorola Smart Networks Developer Forum 2003 , Dallas, TX (Mar .). Porter, J. 2003. RapidIO technical deep dive 2: parallel and serial PHY. Motorola Smart Networks Developer Forum 2003, Dallas, TX (Mar.)."},{"key":"e_1_2_1_22_1","unstructured":"Praesum Communications 2001. RapidIO physical layer 8\/16 LP-LVDS core product brief. Product brief.  Praesum Communications 2001. RapidIO physical layer 8\/16 LP-LVDS core product brief. Product brief."},{"key":"e_1_2_1_23_1","unstructured":"Rapidio Trade Association 2002a. RapidIO interconnect specification documentation overview. Specification.  Rapidio Trade Association 2002a. RapidIO interconnect specification documentation overview. Specification."},{"key":"e_1_2_1_24_1","unstructured":"Rapidio Trade Association 2002b. RapidIO interconnect specification part V: globally shared memory logical specification. Specification.  Rapidio Trade Association 2002b. RapidIO interconnect specification part V: globally shared memory logical specification. Specification."},{"key":"e_1_2_1_25_1","unstructured":"Rapidio Trade Association 2002c. RapidIO interconnect specification part VI: physical layer 1x\/4x LP serial specification. Specification.  Rapidio Trade Association 2002c. RapidIO interconnect specification part VI: physical layer 1x\/4x LP serial specification. Specification."},{"key":"e_1_2_1_26_1","unstructured":"Rapidio Trade Association 2002d. RapidIO interconnect specification part VIII: error management extensions specification. Specification.  Rapidio Trade Association 2002d. RapidIO interconnect specification part VIII: error management extensions specification. Specification."},{"key":"e_1_2_1_27_1","unstructured":"Rapidio Trade Association 2002e. RapidIO hardware inter-operability platform (HIP) document. Specification.  Rapidio Trade Association 2002e. RapidIO hardware inter-operability platform (HIP) document. Specification."},{"key":"e_1_2_1_28_1","unstructured":"Rapidio Trade Association 2002f. RapidIO interconnect specification parts I-IV. Specification.  Rapidio Trade Association 2002f. RapidIO interconnect specification parts I-IV. Specification."},{"key":"e_1_2_1_29_1","unstructured":"Rapidio Trade Association 2005a. RapidIO interconnect specification part IX: flow control extensions specification. Specification.  Rapidio Trade Association 2005a. RapidIO interconnect specification part IX: flow control extensions specification. Specification."},{"key":"e_1_2_1_30_1","unstructured":"Rapidio Trade Association 2005b. RapidIO interconnect specification part X: data streaming logical layer phase I. Specification.  Rapidio Trade Association 2005b. RapidIO interconnect specification part X: data streaming logical layer phase I. Specification."},{"key":"e_1_2_1_31_1","unstructured":"Rapidio Trade Association 2005c. RapidIO interconnect specification part XI: multicast extensions. Specification.  Rapidio Trade Association 2005c. RapidIO interconnect specification part XI: multicast extensions. Specification."},{"key":"e_1_2_1_32_1","unstructured":"Redswitch 2002. RS-1001 16-port serial\/parallel RapidIO switch and PCI bridge. Product brief.  Redswitch 2002. RS-1001 16-port serial\/parallel RapidIO switch and PCI bridge. Product brief."},{"key":"e_1_2_1_33_1","volume-title":"11th IEEE\/ACM International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), Orlando, FL (Oct.). 207--212","author":"Schocht G.","unstructured":"Schocht , G. , Troxel , I. , Farhangian , K. , Unger , P. , Zinn , D. , Mick , C. , George , A. , and Salzwedel , H . 2003. System-level simulation modeling with MLDesigner . In 11th IEEE\/ACM International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), Orlando, FL (Oct.). 207--212 . Schocht, G., Troxel, I., Farhangian, K., Unger, P., Zinn, D., Mick, C., George, A., and Salzwedel, H. 2003. System-level simulation modeling with MLDesigner. In 11th IEEE\/ACM International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), Orlando, FL (Oct.). 207--212."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1177\/003754979205800203"},{"key":"e_1_2_1_35_1","volume-title":"RapidIO technical deep dive I: architecture and protocol. Motorola Smart Networks Developer Forum","author":"Shippen G.","year":"2003","unstructured":"Shippen , G. 2003. RapidIO technical deep dive I: architecture and protocol. Motorola Smart Networks Developer Forum 2003 , Dallas, TX (Mar .). Shippen, G. 2003. RapidIO technical deep dive I: architecture and protocol. Motorola Smart Networks Developer Forum 2003, Dallas, TX (Mar.)."},{"key":"e_1_2_1_36_1","volume-title":"Adaptive Sensor Array Processing Workshop, Lexington, MA (Mar.)","author":"Skalabrin M.","unstructured":"Skalabrin , M. and Einstein , T . 1996. STAP processing on multiprocessor systems: distribution of 3-D data sets and processor allocation for efficient interprocessor communication . In Adaptive Sensor Array Processing Workshop, Lexington, MA (Mar.) Skalabrin, M. and Einstein, T. 1996. STAP processing on multiprocessor systems: distribution of 3-D data sets and processor allocation for efficient interprocessor communication. In Adaptive Sensor Array Processing Workshop, Lexington, MA (Mar.)"},{"key":"e_1_2_1_37_1","unstructured":"Tundra Semiconductor Corporation 2003a. Tsi500 parallel RapidIO multi-port switch. Feature sheet.  Tundra Semiconductor Corporation 2003a. Tsi500 parallel RapidIO multi-port switch. Feature sheet."},{"key":"e_1_2_1_38_1","unstructured":"Tundra Semiconductor Corporation 2003b. Tsi500 parallel RapidIO multi-port switch. User Manual.  Tundra Semiconductor Corporation 2003b. Tsi500 parallel RapidIO multi-port switch. User Manual."},{"key":"e_1_2_1_39_1","unstructured":"Xilinx 2003. LogiCORE RapidIO 8-bit port physical layer interface design guide. Design guide.  Xilinx 2003. LogiCORE RapidIO 8-bit port physical layer interface design guide. Design guide."},{"key":"e_1_2_1_40_1","unstructured":"Xilinx 2002a. Xilinx solutions for RapidIO. Product overview.  Xilinx 2002a. Xilinx solutions for RapidIO. Product overview."},{"key":"e_1_2_1_41_1","unstructured":"Xilinx 2003b. Xilinx LogiCORE RapidIO logical (I\/O) and transport layer interface DS242 (v1.3). Product specification.  Xilinx 2003b. Xilinx LogiCORE RapidIO logical (I\/O) and transport layer interface DS242 (v1.3). Product specification."},{"key":"e_1_2_1_42_1","unstructured":"Xilinx 2003c. Xilinx LogiCORE RapidIO 8-bit port physical layer interface DS243 (v1.3). Product specification.  Xilinx 2003c. Xilinx LogiCORE RapidIO 8-bit port physical layer interface DS243 (v1.3). Product specification."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1324969.1324970","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1324969.1324970","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:39:27Z","timestamp":1750253967000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1324969.1324970"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,12]]},"references-count":42,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2007,12]]}},"alternative-id":["10.1145\/1324969.1324970"],"URL":"https:\/\/doi.org\/10.1145\/1324969.1324970","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,12]]},"assertion":[{"value":"2005-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2006-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2007-12-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}