{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,2]],"date-time":"2026-10-02T12:34:38Z","timestamp":1790944478127,"version":"4.1.0"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,9,16]],"date-time":"2007-09-16T00:00:00Z","timestamp":1189900800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,9,16]]},"DOI":"10.1145\/1327171.1327177","type":"proceedings-article","created":{"date-parts":[[2008,1,3]],"date-time":"2008-01-03T18:13:30Z","timestamp":1199384010000},"page":"49-55","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Code-size conscious pipelining of imperfectly nested loops"],"prefix":"10.1145","author":[{"given":"Mohammed","family":"Fellahi","sequence":"first","affiliation":[{"name":"INRIA Futurs, Orsay, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Albert","family":"Cohen","sequence":"additional","affiliation":[{"name":"INRIA Futurs, Orsay, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sid","family":"Touati","sequence":"additional","affiliation":[{"name":"University of Versailles, France"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2007,9,16]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Morgan and Kaufman","author":"Allen R.","year":"2002","unstructured":"R. Allen and K. Kennedy . Optimizing Compilers for Modern Architectures . Morgan and Kaufman , 2002 . R. Allen and K. Kennedy. Optimizing Compilers for Modern Architectures. Morgan and Kaufman, 2002."},{"issue":"2","key":"e_1_3_2_1_2_1","first-page":"155","article-title":"Ptolemy: A framework for simulating and prototyping heterogenous systems","volume":"4","author":"Buck J.","year":"1994","unstructured":"J. Buck , S. Ha , E. A. Lee , and D. G. Messerschmitt . Ptolemy: A framework for simulating and prototyping heterogenous systems . Int. J. in Computer Simulation , 4 ( 2 ): 155 -- 182 , 1994 . J. Buck, S. Ha, E. A. Lee, and D. G. Messerschmitt. Ptolemy: A framework for simulating and prototyping heterogenous systems. Int. J. in Computer Simulation, 4(2):155--182, 1994.","journal-title":"Int. J. in Computer Simulation"},{"key":"e_1_3_2_1_3_1","volume-title":"Proceedings of the 29th Hawaii Intl. Conf. on System Sciences (HICSS'96)","volume":"1996","author":"Carr S.","unstructured":"S. Carr , C. Ding , and P. Sweany . Improving software pipelining with unroll-and-jam . In Proceedings of the 29th Hawaii Intl. Conf. on System Sciences (HICSS'96) Volume 1: Software Technology and Architecture. IEEE, 1996 . S. Carr, C. Ding, and P. Sweany. Improving software pipelining with unroll-and-jam. In Proceedings of the 29th Hawaii Intl. Conf. on System Sciences (HICSS'96) Volume 1: Software Technology and Architecture. IEEE, 1996."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006244"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/552524"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626497000383"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/70082.68185"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299109"},{"key":"e_1_3_2_1_9_1","first-page":"Q4","article-title":"An overview of the Intel IA-64 compiler","author":"Dulong C.","year":"1999","unstructured":"C. Dulong , R. Krishnaiyer , D. Kulkarni , D. Lavery , W. Li , J. Ng , and D. Sehr . An overview of the Intel IA-64 compiler . Intel Technical Journal , Q4 , 1999 . C. Dulong, R. Krishnaiyer, D. Kulkarni, D. Lavery, W. Li, J. Ng, and D. Sehr. An overview of the Intel IA-64 compiler. Intel Technical Journal, Q4, 1999.","journal-title":"Intel Technical Journal"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.5009446"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/55364.55406"},{"key":"e_1_3_2_1_12_1","first-page":"281","volume-title":"LCPC'5 Fifth Workshop on Languages and Compilers for Parallel Computing, LNCS 757","author":"Gao G.","year":"1992","unstructured":"G. Gao , R., V. Sarkar , and R. Thekkath . Collective loop fusion for array contraction . In LCPC'5 Fifth Workshop on Languages and Compilers for Parallel Computing, LNCS 757 , pages 281 -- 295 , New Haven , august 1992 . G. Gao, R., V. Sarkar, and R. Thekkath. Collective loop fusion for array contraction. In LCPC'5 Fifth Workshop on Languages and Compilers for Parallel Computing, LNCS 757, pages 281--295, New Haven, august 1992."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-006-0012-3"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168877"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/780732.780747"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01759032"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/158511.158515"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/233561.233564"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196114"},{"key":"e_1_3_2_1_20_1","first-page":"91","volume-title":"Proc. of ProRISC, 15th annual Workshop of Circuits, System and Signal Processing","author":"Moonen A.","year":"2004","unstructured":"A. Moonen , M. Bekooij , and J. van Meerbergen . Timing analysis model for network based multiprocessor systems . In Proc. of ProRISC, 15th annual Workshop of Circuits, System and Signal Processing , pages pages 91 -- 99 , Veldhoven, The Netherlands , Nov. 2004 . A. Moonen, M. Bekooij, and J. van Meerbergen. Timing analysis model for network based multiprocessor systems. In Proc. of ProRISC, 15th annual Workshop of Circuits, System and Signal Processing, pages pages 91--99, Veldhoven, The Netherlands, Nov. 2004."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSMCA.2005.851140"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"e_1_3_2_1_24_1","volume-title":"Proceedings of the International Symposium on Code generation and Optimization(CGO'04)","author":"Rong H.","year":"2004","unstructured":"H. Rong , Z. Tang , R. Govindarajan , A. Douillet , and G. R. Gao . Single-dimension software pipelining for multi-dimensional loops . In Proceedings of the International Symposium on Code generation and Optimization(CGO'04) , Mar. 2004 . H. Rong, Z. Tang, R. Govindarajan, A. Douillet, and G. R. Gao. Single-dimension software pipelining for multi-dimensional loops. In Proceedings of the International Symposium on Code generation and Optimization(CGO'04), Mar. 2004."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291015"},{"key":"e_1_3_2_1_26_1","volume-title":"Proceedings of the International Conference on Compiler Construction (CC)","author":"Touati S.","year":"2003","unstructured":"S. Touati and C. Eisenbeis . Early Control of Register Pressure for Software Pipelined Loops . In Proceedings of the International Conference on Compiler Construction (CC) , Warsaw, Poland , Apr. 2003 . Springer-Verlag. S. Touati and C. Eisenbeis. Early Control of Register Pressure for Software Pipelined Loops. In Proceedings of the International Conference on Compiler Construction (CC), Warsaw, Poland, Apr. 2003. Springer-Verlag."},{"key":"e_1_3_2_1_27_1","first-page":"500","volume-title":"Languages and Compilers for Parallel Computers (LCPC'93), number 768 in LNCS","author":"Tu P.","year":"1993","unstructured":"P. Tu and D. Padua . Automatic array privatization . In Languages and Compilers for Parallel Computers (LCPC'93), number 768 in LNCS , pages 500 -- 521 , Portland , Oregon, Aug . 1993 . P. Tu and D. Padua. Automatic array privatization. In Languages and Compilers for Parallel Computers (LCPC'93), number 768 in LNCS, pages 500--521, Portland, Oregon, Aug. 1993."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299056"},{"key":"e_1_3_2_1_29_1","first-page":"17","volume-title":"ASAP","author":"Verdoolaege S.","year":"2003","unstructured":"S. Verdoolaege , M. Bruynooghe , G. Janssens , and F. Catthoor . Multidimentsional incremetal loops fusion for data locality . In ASAP , pages 17 -- 27 , 2003 . S. Verdoolaege, M. Bruynooghe, G. Janssens, and F. Catthoor. Multidimentsional incremetal loops fusion for data locality. In ASAP, pages 17--27, 2003."}],"event":{"name":"PACT07: International Conference on Parallel Architectures and Compilation Techniques","location":"Brasov Romania","acronym":"PACT07","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1327171.1327177","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1327171.1327177","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:25Z","timestamp":1750254985000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1327171.1327177"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,9,16]]},"references-count":28,"alternative-id":["10.1145\/1327171.1327177","10.1145\/1327171"],"URL":"https:\/\/doi.org\/10.1145\/1327171.1327177","relation":{},"subject":[],"published":{"date-parts":[[2007,9,16]]},"assertion":[{"value":"2007-09-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}