{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:35Z","timestamp":1750307795632,"version":"3.41.0"},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2007,9,1]],"date-time":"2007-09-01T00:00:00Z","timestamp":1188604800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,9]]},"abstract":"<jats:p>In this work we study how cache complexity impacts energy and performance in high performance processors. Moreover, we estimate cache energy budget for two high performance processors. We calculate energy and latency break-even points for realistic and ideal cache organizations for different applications. We show that design efforts made to reduce cache miss rate are only justifiable from the energy and performance point of view only if the associated latency and energy overhead remain below the calculated break-even points.<\/jats:p>\n          <jats:p>Furthermore, we show that, for the processors and applications studied here, the instruction cache has a lower latency break-even point compared to the data cache. However, investing energy in the data cache is likely to result in better energy efficiency compared to the instruction cache.<\/jats:p>\n          <jats:p>We also study alternative cache configurations for different processors and investigate if such alternatives would improve energy efficiency.<\/jats:p>","DOI":"10.1145\/1327312.1327316","type":"journal-article","created":{"date-parts":[[2007,12,21]],"date-time":"2007-12-21T14:52:36Z","timestamp":1198248756000},"page":"13-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Investigating cache energy and latency break-even points in high performance processors"],"prefix":"10.1145","volume":"35","author":[{"given":"Kaveh Jokar","family":"Deris","sequence":"first","affiliation":[{"name":"University of Victoria, Victoria, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amirali","family":"Baniasadi","sequence":"additional","affiliation":[{"name":"University of Victoria, Victoria, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.52"},{"key":"e_1_2_1_2_1","volume-title":"proc. of HPCA","author":"Jeong J.","year":"2003","unstructured":"J. Jeong , M. Dubois , \"Cost-Sensitive Cache Replacement Algorithms\" , In proc. of HPCA 2003 , J. Jeong, M. Dubois, \"Cost-Sensitive Cache Replacement Algorithms\", In proc. of HPCA 2003,"},{"key":"e_1_2_1_3_1","volume-title":"IEEE PACT","author":"Wang Zh.","year":"2002","unstructured":"Zh. Wang , K. McKinley , A. Rosenberg , C. Weems , \"Using the Compiler to Improve Cache Replacement Decisions\" , In IEEE PACT 2002 , 199-- Zh. Wang, K. McKinley, A. Rosenberg, C. Weems, \"Using the Compiler to Improve Cache Replacement Decisions\", In IEEE PACT 2002, 199--"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.130"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.41"},{"key":"e_1_2_1_6_1","unstructured":"M. Co D. Weikle and K. Skadron. \"A Break-Even Formulation for Evaluating Branch Predictor Energy Efficiency.\" In 2005 Workshop on Complexity-Effective Design (WCED) held in conjunction with the 32nd Annual ACM\/IEEE International Symposium on Computer Architecture (ISCA) 2005.  M. Co D. Weikle and K. Skadron. \"A Break-Even Formulation for Evaluating Branch Predictor Energy Efficiency.\" In 2005 Workshop on Complexity-Effective Design (WCED) held in conjunction with the 32nd Annual ACM\/IEEE International Symposium on Computer Architecture (ISCA) 2005."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/11596356_9"},{"volume-title":"ICDCS 2002","author":"Yin L.","key":"e_1_2_1_8_1","unstructured":"L. Yin , G. Cao , C. Das , A. Ashraf , 'Power-Aware Prefetch in Mobile Environments\" , ICDCS 2002 L. Yin, G. Cao, C. Das, A. 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Montanaro , A 160 MHz, 32b 0.5 W CMOS RISC Microprocessor , In IEEE ISSCC 1996 Digest of Papers , 1996 . J. Montanaro, et al. A 160 MHz, 32b 0.5 W CMOS RISC Microprocessor, In IEEE ISSCC 1996 Digest of Papers, 1996."},{"key":"e_1_2_1_15_1","volume-title":"Computer Architecture a Quantitative Approach","author":"Hennessy J.","year":"1996","unstructured":"J. Hennessy , and D. Patterson , \" Computer Architecture a Quantitative Approach \", Morgan Kaufmann publishing, Inc, 1996 . J. Hennessy, and D. Patterson, \"Computer Architecture a Quantitative Approach\", Morgan Kaufmann publishing, Inc, 1996."},{"key":"e_1_2_1_16_1","first-page":"377","volume-title":"13th Symp. Integrated Circuits and Systems Design, IEEE Press","author":"Tseng J.","year":"2000","unstructured":"J. Tseng and K. Asanovic , \" Energy-Efficient Register Access,\" Proc . 13th Symp. Integrated Circuits and Systems Design, IEEE Press , 2000 , pp. 377 -- 382 . J. Tseng and K. Asanovic, \"Energy-Efficient Register Access,\" Proc. 13th Symp. Integrated Circuits and Systems Design, IEEE Press, 2000, pp. 377--382."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313871"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360150"},{"volume-title":"High-Performance Caches\", tech. report TR-01-01-02","author":"Azizi N.","key":"e_1_2_1_19_1","unstructured":"N. Azizi , \" Asymmetric-Cell Caches: Exploiting Bit Value Biases to Reduce Leakage Power in Deep-Submicron , High-Performance Caches\", tech. report TR-01-01-02 , ECE Computer Group , Univ . of Toronto. N. Azizi et al., \"Asymmetric-Cell Caches: Exploiting Bit Value Biases to Reduce Leakage Power in Deep-Submicron, High-Performance Caches\", tech. report TR-01-01-02, ECE Computer Group, Univ. of Toronto."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566422"},{"volume-title":"proc. of the international symposium on Microarchitecture.","author":"Rivers J.","key":"e_1_2_1_21_1","unstructured":"J. Rivers , G. Tyson , E. Davidson , T. Austin . \"On high-bandwidth data cache design for multi-issue processors\" December 1997 . In proc. of the international symposium on Microarchitecture. J. Rivers, G. Tyson, E. Davidson, T. Austin. \"On high-bandwidth data cache design for multi-issue processors\" December 1997. In proc. of the international symposium on Microarchitecture."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263595"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379268"},{"key":"e_1_2_1_24_1","volume-title":"International Symposium on Computer Architecture, 2002","author":"Flautner K.","year":"2002","unstructured":"K. Flautner , N. Kim , S. Martin , D. Blaauw , T. Mudge , \"Drowsy Caches : Simple Techniques for Reducing Leakage Power \". International Symposium on Computer Architecture, 2002 , June 2002 . K. Flautner, N. Kim, S. Martin, D. Blaauw, T. Mudge, \"Drowsy Caches: Simple Techniques for Reducing Leakage Power\". International Symposium on Computer Architecture, 2002, June 2002."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1327312.1327316","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1327312.1327316","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:25Z","timestamp":1750254985000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1327312.1327316"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,9]]},"references-count":24,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2007,9]]}},"alternative-id":["10.1145\/1327312.1327316"],"URL":"https:\/\/doi.org\/10.1145\/1327312.1327316","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2007,9]]},"assertion":[{"value":"2007-09-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}