{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:32:11Z","timestamp":1761323531579,"version":"3.41.0"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2007,9,1]],"date-time":"2007-09-01T00:00:00Z","timestamp":1188604800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2007,9]]},"abstract":"<jats:p>D-NUCA caches are cache memories that, thanks to banked organization, broadcast search and promotion\/demotion mechanism, are able to tolerate the increasing wire delay effects introduced by technology scaling. As a consequence, they will outperform conventional caches (UCA, Uniform Cache Architectures) in future generation cores.<\/jats:p>\n          <jats:p>Due to the promotion\/demotion mechanism, we have found that, in a D-NUCA cache, the distribution of hits on the ways varies across applications as well as across different execution phases within a single application. In this paper, we show how such a behavior can be utilized to improve D-NUCA power efficiency as well as to decrease its access latencies. In particular, we propose a new D-NUCA structure, called Way Adaptable D-NUCA cache, in which the number of active (i.e. powered-on) ways is dynamically adapted to the need of the running application. Our initial evaluation shows that a consistent reduction of both the average number of active ways (42% in average) and the number of bank access requests (29% in average) is achieved, without significantly affecting the IPC.<\/jats:p>","DOI":"10.1145\/1327312.1327321","type":"journal-article","created":{"date-parts":[[2007,12,21]],"date-time":"2007-12-21T14:52:36Z","timestamp":1198248756000},"page":"53-58","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Improving power efficiency of D-NUCA caches"],"prefix":"10.1145","volume":"35","author":[{"given":"A.","family":"Bardine","sequence":"first","affiliation":[{"name":"Universit\u00e0 di Pisa, Via Diotisalvi, Pisa (Italy)"}]},{"given":"P.","family":"Foglia","sequence":"additional","affiliation":[{"name":"Universit\u00e0 di Pisa, Via Diotisalvi, Pisa (Italy)"}]},{"given":"G.","family":"Gabrielli","sequence":"additional","affiliation":[{"name":"Universit\u00e0 di Pisa, Via Diotisalvi, Pisa (Italy)"}]},{"given":"C. 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