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In recent years a few checkpoint based microarchitectures have been proposed. In comparison with ROB-based processors, checkpoint processors are scalable and highly resource efficient. Unfortunately, in these proposals the misprediction recovery time is proportional to the instruction queue size.<\/jats:p>\n          <jats:p>In this paper we analyze methods to reduce the misprediction recovery time. We propose a new register file management scheme and techniques to selectively flush the instruction queue and the load store queue, and to isolate deeply pipelined execution units. The result is a novel checkpoint processor with Constant misprediction RollBack time (CRB). We further present a streamlined, cost-efficient solution, which saves complexity at the price of slightly lower performance.<\/jats:p>","DOI":"10.1145\/1328195.1328201","type":"journal-article","created":{"date-parts":[[2008,2,8]],"date-time":"2008-02-08T15:32:16Z","timestamp":1202484736000},"page":"1-32","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Hiding the misprediction penalty of a resource-efficient high-performance processor"],"prefix":"10.1145","volume":"4","author":[{"given":"Amit","family":"Golander","sequence":"first","affiliation":[{"name":"Tel-Aviv University, Tel-Aviv, Israel"}]},{"given":"Shlomo","family":"Weiss","sequence":"additional","affiliation":[{"name":"Tel-Aviv University, Tel-Aviv, Israel"}]}],"member":"320","published-online":{"date-parts":[[2008,1,30]]},"reference":[{"volume-title":"Proc. of the 36th Annual Int'l Symp. on Microarchitecture. 423--434","author":"Akkary H.","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1044823.1044826"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514223"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.51"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/377792.377854"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1138035.1138038"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305175"},{"volume-title":"Proc. of the 12th IEEE Int'l Symp. on High-Performance Computer Architecture. 266--277","author":"Chung J.","key":"e_1_2_1_9_1"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2003.4"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10008"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1044823.1044825"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2005.42"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.46"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10004"},{"volume-title":"Proc. of the Int'l Conf. on Computer Design. 236--243","author":"Grochowski E.","key":"e_1_2_1_16_1"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279376"},{"volume-title":"Proc. of the 31st Annual Int'l Symp. on Computer Architecture. 102--113","author":"Hammond L.","key":"e_1_2_1_18_1"},{"volume-title":"Tech. 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