{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,22]],"date-time":"2026-04-22T19:55:41Z","timestamp":1776887741409,"version":"3.51.2"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2008,3,1]],"date-time":"2008-03-01T00:00:00Z","timestamp":1204329600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["CCF-0429745"],"award-info":[{"award-number":["CCF-0429745"]}],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2008,3]]},"abstract":"<jats:p>\n            Reversible logic has applications in low-power computing and quantum computing. Most reversible logic synthesis methods are tied to particular gate types, and cannot synthesize large functions. This article extends RMRLS, a reversible logic synthesis tool, to include additional gate types. While classic RMRLS can synthesize functions using NOT, CNOT, and\n            <jats:italic>n<\/jats:italic>\n            -bit Toffoli gates, our work details the inclusion of\n            <jats:italic>n<\/jats:italic>\n            -bit Fredkin and Peres gates. We find that these additional gates reduce the average gate count for three-variable functions from 6.10 to 4.56, and improve the synthesis results of many larger functions, both in terms of gate count and quantum cost.\n          <\/jats:p>","DOI":"10.1145\/1330521.1330523","type":"journal-article","created":{"date-parts":[[2008,4,8]],"date-time":"2008-04-08T15:40:00Z","timestamp":1207669200000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":53,"title":["Reversible logic synthesis with Fredkin and Peres gates"],"prefix":"10.1145","volume":"4","author":[{"given":"James","family":"Donald","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ"}]},{"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}]}],"member":"320","published-online":{"date-parts":[[2008,4,7]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe (DATE)","volume":"2","author":"Agrawal A."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.52.3457"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.176.0525"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1364\/OL.12.000542"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1080\/00207219408925927"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 211--214","author":"Dueck G. W."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01857727"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.871622"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996790"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514026"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996789"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.53.0183"},{"key":"e_1_2_1_13_1","unstructured":"Margolus N. 1988. Physics and computation. Ph.D. dissertation Massachusetts Institute of Technology Cambridge MA.  Margolus N. 1988. Physics and computation. Ph.D. dissertation Massachusetts Institute of Technology Cambridge MA."},{"key":"e_1_2_1_14_1","unstructured":"Maslov D. 2003. Reversible logic synthesis. Ph.D. dissertation The University of New Brunswick Fredericton New Brunswick Canada.   Maslov D. 2003. Reversible logic synthesis. Ph.D. dissertation The University of New Brunswick Fredericton New Brunswick Canada."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.836735"},{"key":"e_1_2_1_16_1","unstructured":"Maslov D. Dueck G. W. and Scott N. 2007. Reversible logic synthesis benchmarks page. http:\/\/www.cs.uvic.ca\/~dmaslov\/.  Maslov D. Dueck G. W. and Scott N. 2007. Reversible logic synthesis benchmarks page. http:\/\/www.cs.uvic.ca\/~dmaslov\/."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847911"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009900"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2002.1186906"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775915"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.32.3266"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the EUROMICRO Symposium on Digital Systems Design, 245--252","author":"Perkowski M."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811448"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.53.2855"},{"key":"e_1_2_1_25_1","doi-asserted-by":"crossref","unstructured":"Toffoli T. 1980. Reversible computing. In Automata Languages and Programming J. W. de Bakker and J. van Leeuwen eds. Springer 632--644.   Toffoli T. 1980. Reversible computing. In Automata Languages and Programming J. W. de Bakker and J. van Leeuwen eds. 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