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Syst."],"published-print":{"date-parts":[[2008,2]]},"abstract":"<jats:p>Real-time multimedia applications are increasingly being mapped onto MPSoC (multiprocessor system-on-chip) platforms containing hardware--software IPs (intellectual property), along with a library of common scheduling policies such as EDF, RM. The choice of a scheduling policy for each IP is a key decision that greatly affects the design's ability to meet real-time constraints, and also directly affects the energy consumed by the design. We present a cosynthesis framework for design space exploration that considers heterogeneous scheduling while mapping multimedia applications onto such MPSoCs. In our approach, we select a suitable scheduling policy for each IP such that system energy is minimized\u2014our framework also includes energy-reduction techniques utilizing dynamic power management. Experimental results on a realistic multimode multimedia terminal application demonstrate that our approach enables us to select design points with up to 60.5% reduced energy for a given area constraint, while meeting all real-time requirements. More importantly, our approach generates a tradeoff space between energy and cost allowing designers to comparatively evaluate multiple system level mappings.<\/jats:p>","DOI":"10.1145\/1331331.1331333","type":"journal-article","created":{"date-parts":[[2008,2,28]],"date-time":"2008-02-28T14:02:33Z","timestamp":1204207353000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":21,"title":["Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies"],"prefix":"10.1145","volume":"7","author":[{"given":"Minyoung","family":"Kim","sequence":"first","affiliation":[{"name":"University of California, Irvine, Irvine, California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudarshan","family":"Banerjee","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nikil","family":"Dutt","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nalini","family":"Venkatasubramanian","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, California"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,1,29]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303079"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.845896"},{"volume-title":"RAW '06: Proceedings of the 20th International Parallel &amp; Distributed Processing Symposium Reconfigurable Architectures Workshop.","author":"Bijlsma T.","key":"e_1_2_1_3_1","unstructured":"Bijlsma , T. , Wolkotte , P. T. , and Smit , G. J . 2006. An optimal architecture for a DDC . In RAW '06: Proceedings of the 20th International Parallel &amp; Distributed Processing Symposium Reconfigurable Architectures Workshop. Bijlsma, T., Wolkotte, P. T., and Smit, G. J. 2006. An optimal architecture for a DDC. In RAW '06: Proceedings of the 20th International Parallel &amp; Distributed Processing Symposium Reconfigurable Architectures Workshop."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:TIME.0000048932.30002.d9"},{"volume-title":"DAC '04: Proceedings of the 19th Annual Conference on Design Automation. 241--247","author":"Fiduccia C. M.","key":"e_1_2_1_5_1","unstructured":"Fiduccia , C. M. and Mattheyses , R. M . 1982. A linear time heuristic for improved network partitions . In DAC '04: Proceedings of the 19th Annual Conference on Design Automation. 241--247 . Fiduccia, C. M. and Mattheyses, R. M. 1982. A linear time heuristic for improved network partitions. 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