{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,16]],"date-time":"2026-07-16T23:52:07Z","timestamp":1784245927135,"version":"3.55.0"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2008,1,29]],"date-time":"2008-01-29T00:00:00Z","timestamp":1201564800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000149","name":"Division of Engineering Education and Centers","doi-asserted-by":"publisher","award":["EEC-9523338"],"award-info":[{"award-number":["EEC-9523338"]}],"id":[{"id":"10.13039\/100000149","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["CSR-EHS 0509540"],"award-info":[{"award-number":["CSR-EHS 0509540"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2008,2]]},"abstract":"<jats:p>\n            Dynamic voltage scaling (DVS) is a well-known low-power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time. However, in a DVS system consisting of a DVS processor and multiple devices, slowing down the processor increases the device energy consumption and thereby the system-level energy consumption. In this paper, we first use system-level energy consideration to derive the \u201coptimal \u201d scaling factor by which a task should be scaled if there are no deadline constraints. Next, we develop dynamic task-scheduling algorithms that make use of dynamic processor utilization and optimal scaling factor to determine the speed setting of a task. We present algorithm\n            <jats:italic>duEDF<\/jats:italic>\n            , which reduces the CPU energy consumption and algorithm\n            <jats:italic>duSYS<\/jats:italic>\n            and its reduced preemption version,\n            <jats:italic>duSYS_PC<\/jats:italic>\n            , which reduce the system-level energy. Experimental results on the video-phone task set show that when the CPU power is dominant, algorithm\n            <jats:italic>duEDF<\/jats:italic>\n            results in up to 45% energy savings compared to the non-DVS case. When the CPU power and device power are comparable, algorithms\n            <jats:italic>duSYS<\/jats:italic>\n            and\n            <jats:italic>duSYS_PC<\/jats:italic>\n            achieve up to 25% energy saving compared to CPU energy-efficient algorithm\n            <jats:italic>duEDF<\/jats:italic>\n            , and up to 12% energy saving over the non-DVS scheduling algorithm. However, if the device power is large compared to the CPU power, then we show that a DVS scheme does not result in lowest energy. Finally, a comparison of the performance of algorithms\n            <jats:italic>duSYS<\/jats:italic>\n            and\n            <jats:italic>duSYS_PC<\/jats:italic>\n            show that preemption control has minimal effect on system-level energy reduction.\n          <\/jats:p>","DOI":"10.1145\/1331331.1331341","type":"journal-article","created":{"date-parts":[[2008,2,28]],"date-time":"2008-02-28T14:02:33Z","timestamp":1204207353000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":84,"title":["Energy-efficient dynamic task scheduling algorithms for DVS systems"],"prefix":"10.1145","volume":"7","author":[{"given":"Jianli","family":"Zhuo","sequence":"first","affiliation":[{"name":"Arizona State University, Tempe, Arizona"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chaitali","family":"Chakrabarti","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, Arizona"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2008,1,29]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the IEEE Real-Time Systems Symposium (RTSS). 95--105","author":"Aydin H.","unstructured":"Aydin , H. , Melhem , R. , Moss , D. , and Alvarez , P. M . 2001. Dynamic and aggressive scheduling techniques for power-aware real-time systems . In Proceedings of the IEEE Real-Time Systems Symposium (RTSS). 95--105 . Aydin, H., Melhem, R., Moss, D., and Alvarez, P. M. 2001. Dynamic and aggressive scheduling techniques for power-aware real-time systems. In Proceedings of the IEEE Real-Time Systems Symposium (RTSS). 95--105."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013327"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065814"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383092"},{"key":"e_1_2_1_5_1","unstructured":"Intel Corp. 2004. Intel PXA270 Processor Electrical Mechanical and Thermal Specification. http:\/\/www.intel.com\/design\/pca\/applicationsprocessors\/datashts\/280002.htm.  Intel Corp. 2004. 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In Proceedings of the ACM-SIAM Symposium on Discrete Algorithms (SoDA). 37--46."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996650"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065612"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013261"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the Design Automation and Test in Europe Conference (DATE). 788--794","author":"Kim W.","unstructured":"Kim , W. , Kim , J. , and Min , S . 2002a. A dynamic voltage scaling algorithm for dynamic-priority hard real-time systems using slack time analysis . In Proceedings of the Design Automation and Test in Europe Conference (DATE). 788--794 . Kim, W., Kim, J., and Min, S. 2002a. A dynamic voltage scaling algorithm for dynamic-priority hard real-time systems using slack time analysis. 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In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 219--228."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871605"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013328"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 156--165","author":"Krishna C. M.","unstructured":"Krishna , C. M. and Lee , Y. H . 2000. Voltage-clock-scaling adaptive scheduling techniques for low power in hard real time systems . In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 156--165 . Krishna, C. M. and Lee, Y. H. 2000. Voltage-clock-scaling adaptive scheduling techniques for low power in hard real time systems. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 156--165."},{"key":"e_1_2_1_15_1","unstructured":"Krishna C. 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