{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:34:10Z","timestamp":1761647650862,"version":"3.41.0"},"reference-count":27,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2008,3,1]],"date-time":"2008-03-01T00:00:00Z","timestamp":1204329600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2008,3]]},"abstract":"<jats:p>\n            A new method for improving the timing yield of\nfield-programmable gate array (FPGA) devices affected by intrinsic\nwithin-die variation is proposed. The timing variation is reduced\nby selecting an appropriate configuration for each chip from a set\nof independent configurations, the critical paths of which do not\nshare the same circuit resources on the FPGA. In this article, the\nactual method used to generate independent multiple configurations\nby simply repeating the routing phase is shown, along with the\nresults of Monte Carlo simulation with 10,000 samples. One\nsimulation result showed that the standard deviations of maximum\ncritical path delays are reduced by 28% and 49% for 10% and 30%\nV\n            <jats:sub>th<\/jats:sub>\n            variations (\n            <jats:italic>\u03c3\/ \u03bc<\/jats:italic>\n            ), respectively,\nwith 10 independent configurations. Therefore, the proposed method\nis especially effective for larger V\n            <jats:sub>th<\/jats:sub>\n            variation and is\nexpected to be useful for suppressing the performance variation of\nFPGAs due to the future increase of parameter variation. Another\nsimulation result showed that the effectiveness of the proposed\ntechnique was saturated at the use of 10 or more configurations\nbecause of the degradation of the quality of the configurations.\nTherefore, the use of 10 or fewer configurations is reasonable.\n          <\/jats:p>","DOI":"10.1145\/1331897.1331899","type":"journal-article","created":{"date-parts":[[2009,1,13]],"date-time":"2009-01-13T13:15:48Z","timestamp":1231852548000},"page":"1-31","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations"],"prefix":"10.1145","volume":"1","author":[{"given":"Yohei","family":"Matsumoto","sequence":"first","affiliation":[{"name":"National Institute of Advanced Industrial Science and Technology (AIST) and CREST-Japan Science and Technology Agency"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masakazu","family":"Hioki","sequence":"additional","affiliation":[{"name":"National Institute of Advanced Industrial Science and Technology (AIST) and CREST-Japan Science and Technology Agency"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takashi","family":"Kawanami","sequence":"additional","affiliation":[{"name":"National Institute of Advanced Industrial Science and Technology (AIST) and CREST-Japan Science and Technology Agency"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hanpei","family":"Koike","sequence":"additional","affiliation":[{"name":"National Institute of Advanced Industrial Science and Technology (AIST) and CREST-Japan Science and Technology Agency"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshiyuki","family":"Tsutsumi","sequence":"additional","affiliation":[{"name":"National Institute of Advanced Industrial Science and Technology (AIST), CREST-Japan Science and Technology Agency, and Meiji University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tadashi","family":"Nakagawa","sequence":"additional","affiliation":[{"name":"National Institute of Advanced Industrial Science and Technology (AIST)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshihiro","family":"Sekigawa","sequence":"additional","affiliation":[{"name":"National Institute of Advanced Industrial Science and Technology (AIST)"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,3,17]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.815862"},{"volume-title":"Proceedings of International Conference on Field-Programmable Logic and Applications, 213--222","author":"Betz V.","key":"e_1_2_1_2_1"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for deep-submicron FPGAs. Kluwer Academic Publishers Norwell MA. Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for deep-submicron FPGAs. Kluwer Academic Publishers Norwell MA.","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"e_1_2_1_4_1","unstructured":"Betz V. 2006. FPGA place-and-route challenge. http:\/\/www.eecg.toronto.edu\/~vaughn\/challenge\/ challenge.html. Betz V. 2006. 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IEEE Computer Society Press","author":"Sedcole P.","key":"e_1_2_1_22_1"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.92"},{"key":"e_1_2_1_24_1","unstructured":"STARC 2006. http:\/\/www.starc.jp\/index-e.html  STARC 2006. http:\/\/www.starc.jp\/index-e.html"},{"volume-title":"Proceedings of the Nanotech Workshop on Compact Modeling, 87--92","author":"Watts J.","key":"e_1_2_1_25_1"},{"volume-title":"Proceedings of International Conference on Computer-Aided Design, 29--24","author":"Wong P.","key":"e_1_2_1_26_1"},{"key":"e_1_2_1_27_1","unstructured":"Xilinx Inc. 2005. EasyPath Devices Data Sheet. Xilinx Inc. 2005. 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