{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:35:44Z","timestamp":1750307744960,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2008,4,2]],"date-time":"2008-04-02T00:00:00Z","timestamp":1207094400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2008,4,2]]},"abstract":"<jats:p>An energy-efficient data cache organization for embedded processors with virtual memory is proposed. Application knowledge regarding memory references is used to eliminate most tag translations. A novel tagging scheme is introduced, where both virtual and physical tags coexist. Physical tags and special handling of superset index bits are only used for references to shared regions in order to avoid cache inconsistency. By eliminating the need for most address translations on cache access, a significant power reduction is achieved. We outline an efficient hardware architecture, where the application information is captured in a reprogrammable way and the cache is minimally modified.<\/jats:p>","DOI":"10.1145\/1344418.1344428","type":"journal-article","created":{"date-parts":[[2008,4,29]],"date-time":"2008-04-29T13:01:12Z","timestamp":1209474072000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Heterogeneously tagged caches for low-power embedded systems with virtual memory support"],"prefix":"10.1145","volume":"13","author":[{"given":"Xiangrong","family":"Zhou","sequence":"first","affiliation":[{"name":"University of Maryland, College Park, MD"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter","family":"Petrov","sequence":"additional","affiliation":[{"name":"University of Maryland, College Park, MD"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,4,23]]},"reference":[{"volume-title":"ARM920T Technical Reference Manual","author":"Ltd","key":"e_1_2_1_1_1","unstructured":"ARM, Ltd . 1995. ARM920T Technical Reference Manual . ARM, Ltd. ARM, Ltd. 1995. ARM920T Technical Reference Manual. ARM, Ltd."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/605459.605461"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.1268405"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291036"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.621215"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/301618.301633"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566471"},{"volume-title":"Intel XScale microarchitecture","author":"Intel Corp. 2007.","key":"e_1_2_1_9_1","unstructured":"Intel Corp. 2007. Intel XScale microarchitecture . Intel Corporation . Intel Corp. 2007. Intel XScale microarchitecture. Intel Corporation."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.683005"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/263272.263332"},{"volume-title":"Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), 161--168","author":"Kadayif I.","key":"e_1_2_1_12_1","unstructured":"Kadayif , I. , Nath , P. , Kandemir , M. , and Sivasubramaniam , A . 2004. Compiler-Directed physical address generation for reducing DTLB power . In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), 161--168 . Kadayif, I., Nath, P., Kandemir, M., and Sivasubramaniam, A. 2004. Compiler-Directed physical address generation for reducing DTLB power. In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), 161--168."},{"volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO), 185","author":"Kadayif I.","key":"e_1_2_1_13_1","unstructured":"Kadayif , I. , Sivasubramaniam , A. , Kandemir , M. , Kandiraju , G. , and Chen , G . 2002. Generating physical addresses directly for saving instruction TLB energy . In Proceedings of the International Symposium on Microarchitecture (MICRO), 185 . Kadayif, I., Sivasubramaniam, A., Kandemir, M., Kandiraju, G., and Chen, G. 2002. Generating physical addresses directly for saving instruction TLB energy. In Proceedings of the International Symposium on Microarchitecture (MICRO), 185."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016747"},{"volume-title":"Proceedings of the International Symposium on High-Performance Computer Archtecture (HPCA), 243--252","author":"Kim J.","key":"e_1_2_1_15_1","unstructured":"Kim , J. , Min , S. , Jeon , S. , Ahn , B. , Jeong , D. , and Kim , C . 1995. U-Cache: A cost-effective solution to synonym problem . In Proceedings of the International Symposium on High-Performance Computer Archtecture (HPCA), 243--252 . Kim, J., Min, S., Jeon, S., Ahn, B., Jeong, D., and Kim, C. 1995. U-Cache: A cost-effective solution to synonym problem. In Proceedings of the International Symposium on High-Performance Computer Archtecture (HPCA), 243--252."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.2"},{"volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO), 330--335","author":"Lee C.","key":"e_1_2_1_17_1","unstructured":"Lee , C. , Potkonjak , M. , and Mangione-Smith , W. H . 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems . In Proceedings of the International Symposium on Microarchitecture (MICRO), 330--335 . Lee, C., Potkonjak, M., and Mangione-Smith, W. H. 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the International Symposium on Microarchitecture (MICRO), 330--335."},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design (ICCD), 118--123","author":"Lee J. H.","key":"e_1_2_1_18_1","unstructured":"Lee , J. H. , Lee , J. S. , Jeong , S. , and Kim , S . 2001. A banked-promotion TLB for high performance and low power . In Proceedings of the IEEE International Conference on Computer Design (ICCD), 118--123 . Lee, J. H., Lee, J. S., Jeong, S., and Kim, S. 2001. A banked-promotion TLB for high performance and low power. In Proceedings of the IEEE International Conference on Computer Design (ICCD), 118--123."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086323"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/375977.375978"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065589"},{"volume-title":"Proceedings of the International Symposium on High-Performance Computer Archtecture (HPCA), 51--62","author":"Qiu X.","key":"e_1_2_1_22_1","unstructured":"Qiu , X. and Dubois , M . 2001. Towards virtually-addressed memory hierarchies . In Proceedings of the International Symposium on High-Performance Computer Archtecture (HPCA), 51--62 . Qiu, X. and Dubois, M. 2001. Towards virtually-addressed memory hierarchies. In Proceedings of the International Symposium on High-Performance Computer Archtecture (HPCA), 51--62."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086307"},{"key":"e_1_2_1_24_1","unstructured":"Tarjan D. Thoziyoor S. and Jouppi N. 2006. Cacti 4.0: An integrated cache timing power and area model. Tech. Rep. HP Laboratories Palo Alto California June.  Tarjan D. Thoziyoor S. and Jouppi N. 2006. Cacti 4.0: An integrated cache timing power and area model. Tech. Rep. HP Laboratories Palo Alto California June."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.71"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176760.1176783"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344418.1344428","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1344418.1344428","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:39:04Z","timestamp":1750253944000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344418.1344428"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4,2]]},"references-count":26,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2008,4,2]]}},"alternative-id":["10.1145\/1344418.1344428"],"URL":"https:\/\/doi.org\/10.1145\/1344418.1344428","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2008,4,2]]},"assertion":[{"value":"2007-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2007-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-04-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}