{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,4]],"date-time":"2026-04-04T11:32:19Z","timestamp":1775302339271,"version":"3.50.1"},"reference-count":18,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2008,4,2]],"date-time":"2008-04-02T00:00:00Z","timestamp":1207094400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2008,4,2]]},"abstract":"<jats:p>The Input vector control (IVC) technique is based on the observation that the leakage current in a CMOS logic gate depends on gate input state, and a good input vector is able to minimize leakage when the circuit is in sleep mode. The gate replacement technique is a very effective method to further reduce the leakage current. In this article, we propose a fast heuristic algorithm to find a low-leakage input vector with simultaneous gate replacement. Results on MCNC91 benchmark circuits show that our algorithm produces 14% better leakage current reduction with several orders of magnitude speedup in runtime for large circuits compared to the previous state-of-the-art algorithm. In particular, the average runtime for the ten largest combinational circuits has been dramatically reduced from 1879 seconds to 0.34 seconds.<\/jats:p>","DOI":"10.1145\/1344418.1344430","type":"journal-article","created":{"date-parts":[[2008,4,29]],"date-time":"2008-04-29T13:01:12Z","timestamp":1209474072000},"page":"1-15","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction"],"prefix":"10.1145","volume":"13","author":[{"given":"Lei","family":"Cheng","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deming","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Martin D. F.","family":"Wong","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,4,23]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821546"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation, 167--177","author":"Aloul F. A.","unstructured":"Aloul , F. A. , Hassoun , S. , Sakallah , K. A. , and Blaauw , D . 2002. Robust SAT-based search algorithm for leakage power reduction . In Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation, 167--177 . Aloul, F. A., Hassoun, S., Sakallah, K. A., and Blaauw, D. 2002. Robust SAT-based search algorithm for leakage power reduction. In Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation, 167--177."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/280756.280917"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996774"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882603"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382634"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference, 475--478","author":"Halter J.","unstructured":"Halter , J. and Najm , F . 1997. A gate-level leakage power reduction method for ultra-low-power CMOS circuits . In Proceedings of the IEEE Custom Integrated Circuits Conference, 475--478 . Halter, J. and Najm, F. 1997. A gate-level leakage power reduction method for ultra-low-power CMOS circuits. In Proceedings of the IEEE Custom Integrated Circuits Conference, 475--478."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309976"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.766723"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference, 271--274","author":"Kobayashi T.","unstructured":"Kobayashi , T. and Sakurai , T . 1994. Self-Adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation . In Proceedings of the IEEE Custom Integrated Circuits Conference, 271--274 . Kobayashi, T. and Sakurai, T. 1994. Self-Adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation. In Proceedings of the IEEE Custom Integrated Circuits Conference, 271--274."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the International Solid State Circuits Conference, 182--184","author":"Naffziger S.","unstructured":"Naffziger , S. , Stackhouse , B. , and Grutkowski , T . 2005. The implementation of a 2-core multi-threaded itanium-family processor . In Proceedings of the International Solid State Circuits Conference, 182--184 . Naffziger, S., Stackhouse, B., and Grutkowski, T. 2005. The implementation of a 2-core multi-threaded itanium-family processor. In Proceedings of the International Solid State Circuits Conference, 182--184."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009963"},{"key":"e_1_2_1_14_1","volume-title":"SIS: A system for sequential circuit synthesis. Electronics Research Laboratory Memo UCB\/ERL M92\/41","author":"Sentovich E. M.","year":"1992","unstructured":"Sentovich , E. M. , Singh , K. J. , Lavagno , L. Moon , C. , Murgai , R. , Saldanha , A. , Savoj , H. , Stephan , P. R. , and Brayton , R. K . 1992 . SIS: A system for sequential circuit synthesis. Electronics Research Laboratory Memo UCB\/ERL M92\/41 . University of California at Berkeley . California. Sentovich, E. M., Singh, K. J., Lavagno, L. Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P. R., and Brayton, R. K. 1992. SIS: A system for sequential circuit synthesis. Electronics Research Laboratory Memo UCB\/ERL M92\/41. University of California at Berkeley. California."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277179"},{"key":"e_1_2_1_16_1","unstructured":"Yang S. 1991. Logic synthesis and optimization benchmarks user guide version 3.0. ftp:\/\/mcnc.mcnc.org.  Yang S. 1991. Logic synthesis and optimization benchmarks user guide version 3.0. ftp:\/\/mcnc.mcnc.org."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the IEEE Symposium on VLSI Circuits, 40--41","author":"Ye Y.","unstructured":"Ye , Y. , Borkar , S. , and De , V . 1998. A new technique for standby leakage reduction in high-performance circuits . In Proceedings of the IEEE Symposium on VLSI Circuits, 40--41 . Ye, Y., Borkar, S., and De, V. 1998. A new technique for standby leakage reduction in high-performance circuits. In Proceedings of the IEEE Symposium on VLSI Circuits, 40--41."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065596"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344418.1344430","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1344418.1344430","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:39:04Z","timestamp":1750253944000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344418.1344430"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4,2]]},"references-count":18,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2008,4,2]]}},"alternative-id":["10.1145\/1344418.1344430"],"URL":"https:\/\/doi.org\/10.1145\/1344418.1344430","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,4,2]]},"assertion":[{"value":"2007-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2007-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-04-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}