{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T14:47:56Z","timestamp":1776955676204,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,2,24]],"date-time":"2008-02-24T00:00:00Z","timestamp":1203811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,2,24]]},"DOI":"10.1145\/1344671.1344680","type":"proceedings-article","created":{"date-parts":[[2008,2,28]],"date-time":"2008-02-28T14:02:49Z","timestamp":1204207369000},"page":"47-55","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["WireMap"],"prefix":"10.1145","author":[{"given":"Stephen","family":"Jang","sequence":"first","affiliation":[{"name":"Xilinx Inc., San Jose, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Billy","family":"Chan","sequence":"additional","affiliation":[{"name":"Xilinx Inc., Hong Kong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"Chung","sequence":"additional","affiliation":[{"name":"Xilinx Inc., Toronto, ON, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[{"name":"University of California: Berkeley, Berkeley, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,2,24]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Altera. Stratix III Device Handbook http:\/\/www.altera.com\/literature\/hb\/stx3\/stratix3_handbook.pdf  Altera. Stratix III Device Handbook http:\/\/www.altera.com\/literature\/hb\/stx3\/stratix3_handbook.pdf"},{"key":"e_1_3_2_1_2_1","unstructured":"Altera. \"Improving FPGA performance and area using an adaptive logic module\" http:\/\/www.altera.com\/literature\/cp\/cp-01004.pdf  Altera. \"Improving FPGA performance and area using an adaptive logic module\" http:\/\/www.altera.com\/literature\/cp\/cp-01004.pdf"},{"key":"e_1_3_2_1_3_1","unstructured":"Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification Release 61225. http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/  Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification Release 61225. http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/553523"},{"key":"e_1_3_2_1_5_1","first-page":"519","volume-title":"Proc. ICCAD '05","author":"Chatterjee S.","unstructured":"S. Chatterjee , A. Mishchenko , R. Brayton , X. Wang , and T. Kam , \" Reducing structural bias in technology mapping \", Proc. ICCAD '05 , pp. 519 -- 526 . S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, \"Reducing structural bias in technology mapping\", Proc. ICCAD '05, pp. 519--526."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382677"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"key":"e_1_3_2_1_9_1","volume-title":"Custom Integrated Circuits Conference","author":"Gupta S.","year":"2007","unstructured":"S. Gupta , A. Anderson , L. Farragher , and Q. Wang . \" CAD techniques for power optimization in Virtex-5 FPGAs\", to appear in Proc . Custom Integrated Circuits Conference , 2007 . S. Gupta, A. Anderson, L. Farragher, and Q. Wang. \"CAD techniques for power optimization in Virtex-5 FPGAs\", to appear in Proc. Custom Integrated Circuits Conference, 2007."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.644605"},{"key":"e_1_3_2_1_11_1","first-page":"14","volume-title":"IWLS '04","author":"V.","unstructured":"V. Manohara-rajah, S. D. Brown , and Z. G. Vranesic , \" Heuristics for area minimization in LUT-based FPGA technology mapping,\" Proc . IWLS '04 , pp. 14 -- 21 . V. Manohara-rajah, S. D. Brown, and Z. G. Vranesic, \"Heuristics for area minimization in LUT-based FPGA technology mapping,\" Proc. IWLS '04, pp. 14--21."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117208"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"key":"e_1_3_2_1_14_1","first-page":"358","volume-title":"Proc. IWLS '07","author":"Mishchenko A.","unstructured":"A. Mishchenko , R. Brayton , J.-H. R. Jiang , and S. Jang , \" SAT-based logic optimization and resynthesis \", Proc. IWLS '07 , pp. 358 -- 364 . A. Mishchenko, R. Brayton, J.-H. R. Jiang, and S. Jang, \"SAT-based logic optimization and resynthesis\", Proc. IWLS '07, pp. 358--364."},{"key":"e_1_3_2_1_15_1","volume-title":"Proc. ICCAD '07","author":"Mishchenko A.","unstructured":"A. Mishchenko , S. Cho , S. Chatterjee , and R. Brayton , \" Combinational and sequential mapping with priority cuts \", Proc. ICCAD '07 . A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, \"Combinational and sequential mapping with priority cuts\", Proc. ICCAD '07."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123421"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"key":"e_1_3_2_1_18_1","volume-title":"Department of EECS. UC Berkeley","author":"Sentovich E. M.","year":"1992","unstructured":"E. M. Sentovich , K. J. Singh , L. Lavagno , C. Moon , R. Murgai , A. Saldanha , H. Savoj , P.R. Stephan , R. Brayton , and A. Sangiovanni-Vincentelli . \" SIS: A System for Sequential Circuit Synthesis\". Memorandum No. UCB\/ERL M92\/41 , Department of EECS. UC Berkeley , May 1992 . E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. \"SIS: A System for Sequential Circuit Synthesis\". Memorandum No. UCB\/ERL M92\/41, Department of EECS. UC Berkeley, May 1992."},{"key":"e_1_3_2_1_19_1","unstructured":"Xilinx White Paper. \"Achieving higher system performance with the Virtex--5 family of FPGAs\" http:\/\/direct.xilinx.com\/bvdocs\/whitepapers\/wp245.pdf  Xilinx White Paper. \"Achieving higher system performance with the Virtex--5 family of FPGAs\" http:\/\/direct.xilinx.com\/bvdocs\/whitepapers\/wp245.pdf"}],"event":{"name":"FPGA08: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Monterey California USA","acronym":"FPGA08","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 16th international ACM\/SIGDA symposium on Field programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344671.1344680","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1344671.1344680","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:16Z","timestamp":1750254976000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344671.1344680"}},"subtitle":["FPGA technology mapping for improved routability"],"short-title":[],"issued":{"date-parts":[[2008,2,24]]},"references-count":19,"alternative-id":["10.1145\/1344671.1344680","10.1145\/1344671"],"URL":"https:\/\/doi.org\/10.1145\/1344671.1344680","relation":{},"subject":[],"published":{"date-parts":[[2008,2,24]]},"assertion":[{"value":"2008-02-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}