{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:10:38Z","timestamp":1763467838662,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,2,24]],"date-time":"2008-02-24T00:00:00Z","timestamp":1203811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,2,24]]},"DOI":"10.1145\/1344671.1344684","type":"proceedings-article","created":{"date-parts":[[2008,2,28]],"date-time":"2008-02-28T14:02:49Z","timestamp":1204207369000},"page":"77-86","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":37,"title":["A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs"],"prefix":"10.1145","author":[{"given":"Eric S.","family":"Chung","sequence":"first","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eriko","family":"Nurvitadhi","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James C.","family":"Hoe","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Babak","family":"Falsafi","sequence":"additional","affiliation":[{"name":"Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ken","family":"Mai","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,2,24]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Fast and Portable Dynamic Translator. In Proceedings of USENIX 2005","author":"Bellard F.","year":"2005","unstructured":"F. Bellard . QEMU , a Fast and Portable Dynamic Translator. In Proceedings of USENIX 2005 , FREENIX Track , April 2005 . F. Bellard. QEMU, a Fast and Portable Dynamic Translator. In Proceedings of USENIX 2005, FREENIX Track, April 2005."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1109\/MM.2006.82"},{"unstructured":"Bluespec Inc. http:\/\/www.bluespec.com 2006.  Bluespec Inc. http:\/\/www.bluespec.com 2006.","key":"e_1_3_2_1_3_1"},{"key":"e_1_3_2_1_4_1","volume-title":"ProtoFlex: FPGA-Accelerated Hybrid Functional Simulator. NSF NGS Workshop at IPDPS","author":"Chung E.S.","year":"2007","unstructured":"E.S. Chung , E. Nurvitadhi , J.C. Hoe , K. Mai , B. Falsafi . ProtoFlex: FPGA-Accelerated Hybrid Functional Simulator. NSF NGS Workshop at IPDPS , March 2007 . E.S. Chung, E. Nurvitadhi, J.C. Hoe, K. Mai, B. Falsafi. ProtoFlex: FPGA-Accelerated Hybrid Functional Simulator. NSF NGS Workshop at IPDPS, March 2007."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.5555\/1331699.1331723"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_6_1","DOI":"10.1109\/MDT.2005.30"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.1145\/238788.238822"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1145\/1216919.1216927"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1109\/2.982916"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.1145\/1105734.1105747"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.1145\/201310.201321"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_13_1","DOI":"10.1109\/HPCA.2006.1598110"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1109\/88.473612"},{"key":"e_1_3_2_1_15_1","volume-title":"June","author":"Vahia D.","year":"2007","unstructured":"D. Vahia , P. Hartke . OpenSPARC T1 on Xilinx FPGAs -- Updates. Given on 6\/14\/2007 at RAMP Retreat , June 2007 . D. Vahia, P. Hartke. OpenSPARC T1 on Xilinx FPGAs -- Updates. Given on 6\/14\/2007 at RAMP Retreat, June 2007."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1145\/1216919.1216936"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.1109\/MM.2007.39"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.1109\/MM.2006.79"}],"event":{"sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"acronym":"FPGA08","name":"FPGA08: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Monterey California USA"},"container-title":["Proceedings of the 16th international ACM\/SIGDA symposium on Field programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344671.1344684","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1344671.1344684","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:16Z","timestamp":1750254976000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344671.1344684"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,2,24]]},"references-count":17,"alternative-id":["10.1145\/1344671.1344684","10.1145\/1344671"],"URL":"https:\/\/doi.org\/10.1145\/1344671.1344684","relation":{},"subject":[],"published":{"date-parts":[[2008,2,24]]},"assertion":[{"value":"2008-02-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}