{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T14:13:22Z","timestamp":1761488002571,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,2,24]],"date-time":"2008-02-24T00:00:00Z","timestamp":1203811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,2,24]]},"DOI":"10.1145\/1344671.1344693","type":"proceedings-article","created":{"date-parts":[[2008,2,28]],"date-time":"2008-02-28T14:02:49Z","timestamp":1204207369000},"page":"131-138","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["TORCH"],"prefix":"10.1145","author":[{"given":"Mingjie","family":"Lin","sequence":"first","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abbas","family":"El Gamal","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,2,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5145-4","volume-title":"Architecture and CAD for Deep-Submicron FPGAs","author":"Betz V.","year":"1999","unstructured":"V. Betz , J. Rose , and A. Marquardt , eds. , Architecture and CAD for Deep-Submicron FPGAs . Norwell, MA, USA : Kluwer Academic Publishers , 1999 . V. Betz, J. Rose, and A. Marquardt, eds., Architecture and CAD for Deep-Submicron FPGAs. Norwell, MA, USA: Kluwer Academic Publishers, 1999."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117205"},{"key":"e_1_3_2_1_3_1","unstructured":"Actel Inc. \"Automotive ProASIC3 flash family FPGAs datasheet \" March 2007. Actel Inc. \"Automotive ProASIC3 flash family FPGAs datasheet \" March 2007."},{"key":"e_1_3_2_1_4_1","unstructured":"Xilinx Inc. \"Virtex-II Pro\/Virtex-II Pro X complete data sheet (all four modules) \" March 2007. Xilinx Inc. \"Virtex-II Pro\/Virtex-II Pro X complete data sheet (all four modules) \" March 2007."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887920"},{"key":"e_1_3_2_1_7_1","volume-title":"Segmented channel routing in nearly as efficient as channel routing (and just as hard),\" in Proceedings of the 1991 University of California\/Santa Cruz conference on advanced research in VLSI","author":"Gamal A.E.","year":"1991","unstructured":"A.E. Gamal , J. Greene , and V. Roychowdhury , \" Segmented channel routing in nearly as efficient as channel routing (and just as hard),\" in Proceedings of the 1991 University of California\/Santa Cruz conference on advanced research in VLSI , (Cambridge, MA , USA), pp192--211, MIT Press , 1991 . A.E. Gamal, J. Greene, and V. Roychowdhury, \"Segmented channel routing in nearly as efficient as channel routing (and just as hard),\" in Proceedings of the 1991 University of California\/Santa Cruz conference on advanced research in VLSI, (Cambridge, MA, USA), pp192--211, MIT Press, 1991."},{"key":"e_1_3_2_1_8_1","first-page":"26","volume-title":"CA, USA)","author":"Zhu K.","year":"1992","unstructured":"K. Zhu and D.F. Wong , \" On channel segmentation design for row-based FPGAs,\" in ICCAD '92: Proceedings of the 1992 IEEE\/ACM international conference on computer-aided design, (Los Alamitos , CA, USA) , pp 26 -- 29 , IEEE Computer Society Press , 1992 . K. Zhu and D.F. Wong, \"On channel segmentation design for row-based FPGAs,\" in ICCAD '92: Proceedings of the 1992 IEEE\/ACM international conference on computer-aided design, (Los Alamitos, CA, USA), pp26--29, IEEE Computer Society Press, 1992."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.331404"},{"key":"e_1_3_2_1_10_1","first-page":"496","volume-title":"Channel segmentation design for symmetrical FPGAs,\" in Proceedings of the 1997 International Conference on Computer Design","author":"Mak W.-K.","year":"1996","unstructured":"W.-K. Mak and D.F. Wong , \" Channel segmentation design for symmetrical FPGAs,\" in Proceedings of the 1997 International Conference on Computer Design , pp 496 -- 501 , 1996 . W.-K. Mak and D.F. Wong, \"Channel segmentation design for symmetrical FPGAs,\" in Proceedings of the 1997 International Conference on Computer Design, pp496--501, 1996."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611861"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.924831"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296428"},{"key":"e_1_3_2_1_14_1","first-page":"1954","volume-title":"ICSICT '06. 8th International Conference on","author":"Tu R.","year":"2006","unstructured":"R. Tu and B.-X. Shao , \"Energy\/performance\/area tradeoffs in nanometer FPGA segmented routing architecture,\" in Solid-State and Integrated Circuit Technology, 2006 . ICSICT '06. 8th International Conference on , pp 1954 -- 1956 , 2006 . R. Tu and B.-X. Shao, \"Energy\/performance\/area tradeoffs in nanometer FPGA segmented routing architecture,\" in Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on, pp1954--1956, 2006."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2001.47"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503052"},{"key":"e_1_3_2_1_17_1","first-page":"213","volume-title":"VPR: A new packing, placement and routing tool for FPGA research,\" in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications","author":"Betz V.","year":"1997","unstructured":"V. Betz and J. Rose , \" VPR: A new packing, placement and routing tool for FPGA research,\" in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications , pp 213 -- 222 , 1997 . V. Betz and J. Rose, \"VPR: A new packing, placement and routing tool for FPGA research,\" in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, pp213--222, 1997."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.91"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"Y. Cao T. Sato DSylvester MOrshansky and CHu \"New paradigm of predictive MOSFET and interconnect modeling for early circuit design \" in AIEEE CICC pp201--204 Jun. 2000. Y. Cao T. Sato DSylvester MOrshansky and CHu \"New paradigm of predictive MOSFET and interconnect modeling for early circuit design \" in AIEEE CICC pp201--204 Jun. 2000.","DOI":"10.1109\/CICC.2000.852648"},{"key":"e_1_3_2_1_20_1","volume-title":"Architecture and CAD for Deep-Submicron FPGAs","author":"Betz V.","year":"1990","unstructured":"V. Betz , J. Rose , and A. Marquardt , Architecture and CAD for Deep-Submicron FPGAs . Kluwer Academic Publishers , 1990 . V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1990."}],"event":{"name":"FPGA08: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA08"},"container-title":["Proceedings of the 16th international ACM\/SIGDA symposium on Field programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344671.1344693","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1344671.1344693","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:16Z","timestamp":1750254976000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344671.1344693"}},"subtitle":["a design tool for routing channel segmentation in FPGAs"],"short-title":[],"issued":{"date-parts":[[2008,2,24]]},"references-count":20,"alternative-id":["10.1145\/1344671.1344693","10.1145\/1344671"],"URL":"https:\/\/doi.org\/10.1145\/1344671.1344693","relation":{},"subject":[],"published":{"date-parts":[[2008,2,24]]},"assertion":[{"value":"2008-02-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}