{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:29Z","timestamp":1750307789263,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":33,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,2,24]],"date-time":"2008-02-24T00:00:00Z","timestamp":1203811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,2,24]]},"DOI":"10.1145\/1344671.1344700","type":"proceedings-article","created":{"date-parts":[[2008,2,28]],"date-time":"2008-02-28T14:02:49Z","timestamp":1204207369000},"page":"191-200","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["The amorphous FPGA architecture"],"prefix":"10.1145","author":[{"given":"Mingjie","family":"Lin","sequence":"first","affiliation":[{"name":"Stanford University, Stanford"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,2,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084748.1084750"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117205"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296431"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.475968"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065770"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117221"},{"key":"e_1_3_2_1_7_1","unstructured":"Actel Inc. \"Automotive ProASIC3 flash family FPGAs datasheet \" March 2007.  Actel Inc. \"Automotive ProASIC3 flash family FPGAs datasheet \" March 2007."},{"key":"e_1_3_2_1_8_1","unstructured":"Xilinx \"Virtex-II Pro\/Virtex-II Pro X complete data sheet (all four modules) \" March 2007.  Xilinx \"Virtex-II Pro\/Virtex-II Pro X complete data sheet (all four modules) \" March 2007."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329171"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.205013"},{"key":"e_1_3_2_1_12_1","first-page":"741","volume-title":"IEEE Custom Integr. Circuits Conf.","author":"He J.","year":"1993","unstructured":"J. He and J. Rose , \" Advantages of heterogeneous logic block architectures for FPGAs,\" in Proc . IEEE Custom Integr. Circuits Conf. , pp 741 -- 745 , 1993 . J. He and J. Rose, \"Advantages of heterogeneous logic block architectures for FPGAs,\" in Proc. IEEE Custom Integr. Circuits Conf., pp741--745, 1993."},{"key":"e_1_3_2_1_13_1","first-page":"135","volume-title":"Improving FPGA performance and area using an adaptive logic module.,\" in FPL","author":"Hutton M.","year":"2004","unstructured":"M. Hutton , J. Schleicher , D.M. Lewis , B. Pedersen , R. Yuan , S. Kaptanoglu , G. Baeckler , B. Ratchev , K. Padalia , M. Bourgeault , A. Lee , H. Kim , and R. Saini , \" Improving FPGA performance and area using an adaptive logic module.,\" in FPL , pp 135 -- 144 , 2004 . M. Hutton, J. Schleicher, D.M. Lewis, B. Pedersen, R. Yuan, S. Kaptanoglu, G. Baeckler, B. Ratchev, K. Padalia, M. Bourgeault, A. Lee, H. Kim, and R. Saini, \"Improving FPGA performance and area using an adaptive logic module.,\" in FPL, pp135--144, 2004."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296428"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117219"},{"key":"e_1_3_2_1_16_1","first-page":"309","volume-title":"IEEE Custom Integrated Circuits","author":"Ciccarelli L.","year":"2006","unstructured":"L. Ciccarelli , D. Loparco , M. Innocenti , A. Lodi , C. Mucci , and P. Rolandi , \" A low-power routing architecture optimized for deep sub-micron FPGAs,\" in Conference 2006 , IEEE Custom Integrated Circuits , pp 309 -- 312 , 10-13 Sept. 2006 . L. Ciccarelli, D. Loparco, M. Innocenti, A. Lodi, C. Mucci, and P. Rolandi, \"A low-power routing architecture optimized for deep sub-micron FPGAs,\" in Conference 2006, IEEE Custom Integrated Circuits, pp309--312, 10-13 Sept. 2006."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.331404"},{"key":"e_1_3_2_1_18_1","first-page":"12","volume-title":"Garp: a MIPS processor with a reconfigurable coprocessor,\" in Proceedings of the 5th IEEE Symposium on FCCM","author":"Hauser J.R.","year":"1997","unstructured":"J.R. Hauser and J. Wawrzynek , \" Garp: a MIPS processor with a reconfigurable coprocessor,\" in Proceedings of the 5th IEEE Symposium on FCCM , p 12 , 1997 . J.R. Hauser and J. Wawrzynek, \"Garp: a MIPS processor with a reconfigurable coprocessor,\" in Proceedings of the 5th IEEE Symposium on FCCM, p12, 1997."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968283"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296422"},{"key":"e_1_3_2_1_21_1","unstructured":"Xilinx \"The 40% performance advantage of Virtex-II Pro FPGAs over Competitive PLDs.\" White paper by Xilinx Inc. 2006.  Xilinx \"The 40% performance advantage of Virtex-II Pro FPGAs over Competitive PLDs.\" White paper by Xilinx Inc. 2006."},{"key":"e_1_3_2_1_22_1","unstructured":"Xilinx \"Achieve higher system performance with the Virtex-5 Family of FPGAs.\" White paper by Xilinx Inc. 2006.  Xilinx \"Achieve higher system performance with the Virtex-5 Family of FPGAs.\" White paper by Xilinx Inc. 2006."},{"key":"e_1_3_2_1_23_1","unstructured":"V.M.K. Kamal Chaudhary Philip DCostello \"Programmable circuit optionally configurable as a lookup table or a wide multiplexer \" July 2006.  V.M.K. Kamal Chaudhary Philip DCostello \"Programmable circuit optionally configurable as a lookup table or a wide multiplexer \" July 2006."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065692"},{"key":"e_1_3_2_1_25_1","first-page":"213","volume-title":"VPR: A new packing, placement and routing tool for FPGA research,\" in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications","author":"Betz V.","year":"1997","unstructured":"V. Betz and J. Rose , \" VPR: A new packing, placement and routing tool for FPGA research,\" in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications , pp 213 -- 222 , 1997 . V. Betz and J. Rose, \"VPR: A new packing, placement and routing tool for FPGA research,\" in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, pp213--222, 1997."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382607"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.809660"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.144853"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.475966"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887920"},{"key":"e_1_3_2_1_31_1","volume-title":"CICC. Proceedings of the IEEE 2000","author":"Cao Y.","year":"2000","unstructured":"Y. Cao , T. Sato , M. Orshansky , D. Sylvester , and C. Hu , \" New paradigm of predictive mosfet and interconnect modeling for early circuit simulation,\" in Custom Integrated Circuits Conference, 2000 . CICC. Proceedings of the IEEE 2000 , pp201--204, 2000 . Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, \"New paradigm of predictive mosfet and interconnect modeling for early circuit simulation,\" in Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000, pp201--204, 2000."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503052"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5145-4","volume-title":"Architecture and CAD for Deep-Submicron FPGAs","author":"Betz V.","year":"1999","unstructured":"V. Betz , J. Rose , and A. Marquardt , eds. , Architecture and CAD for Deep-Submicron FPGAs . Norwell, MA, USA : Kluwer Academic Publishers , 1999 . V. Betz, J. Rose, and A. Marquardt, eds., Architecture and CAD for Deep-Submicron FPGAs. Norwell, MA, USA: Kluwer Academic Publishers, 1999."}],"event":{"name":"FPGA08: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA08"},"container-title":["Proceedings of the 16th international ACM\/SIGDA symposium on Field programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344671.1344700","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1344671.1344700","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:16Z","timestamp":1750254976000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1344671.1344700"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,2,24]]},"references-count":33,"alternative-id":["10.1145\/1344671.1344700","10.1145\/1344671"],"URL":"https:\/\/doi.org\/10.1145\/1344671.1344700","relation":{},"subject":[],"published":{"date-parts":[[2008,2,24]]},"assertion":[{"value":"2008-02-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}