{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:35:41Z","timestamp":1750307741663,"version":"3.41.0"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2008,4,1]],"date-time":"2008-04-01T00:00:00Z","timestamp":1207008000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2008,4]]},"abstract":"<jats:p>This paper proposes and evaluates compile time and instruction-set techniques for improving the accuracy of signal-processing algorithms run on fixed-point embedded processors. These techniques are proposed in the context of a profile guided floating- to fixed-point compiler-based conversion process. A novel fixed-point scaling algorithm (IRP) is introduced that exploits correlations between values in a program by applying fixed-point scaling, retaining as much precision as possible without causing overflow. This approach is extended into a more aggressive scaling algorithm (IRP-SA) by leveraging the modulo nature of 2's complement addition and subtraction to discard most significant bits that may not be redundant sign-extension bits. A complementary scaling technique (IDS) is then proposed that enables the fixed-point scaling of a variable to be parameterized, depending upon the context of its definitions and uses. Finally, a novel instruction-set enhancement\u2014<jats:italic>fractional multiplication with internal left shift<\/jats:italic>(FMLS)\u2014is proposed to further leverage interoperand correlations uncovered by the IRP-SA scaling algorithm. FMLS preserves a different subset of the full product's bits than traditional fractional fixed-point or integer multiplication. On average, FMLS combined with IRP-SA improves accuracy on processors with uniform bitwidth register architectures by the equivalent of 0.61 bits of additional precision for a set of signal-processing benchmarks (up to 2 bits). Even without employing FMLS, the IRP-SA scaling algorithm achieves additional accuracy over two previous fixed-point scaling algorithms by averages of 1.71 and 0.49 bits. Furthermore, as FMLS combines multiplication with a scaling shift, it reduces execution time by an average of 9.8%. An implementation of IDS, specialized to single-nested loops, is found to improve accuracy of a lattice filter benchmark by the equivalent of more than 16-bits of precision.<\/jats:p>","DOI":"10.1145\/1347375.1347379","type":"journal-article","created":{"date-parts":[[2008,5,15]],"date-time":"2008-05-15T18:28:05Z","timestamp":1210876085000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy"],"prefix":"10.1145","volume":"7","author":[{"given":"Tor M.","family":"Aamodt","sequence":"first","affiliation":[{"name":"University of British Columbia, Vancouver, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Chow","sequence":"additional","affiliation":[{"name":"University of Toronto, Ontario, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,5,8]]},"reference":[{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/354880.354899"},{"volume-title":"Fixed-Point Optimizer User's Guide. Cadence Design Systems","author":"Alta Group","key":"e_1_2_1_3_1","unstructured":"Alta Group . 1994. Fixed-Point Optimizer User's Guide. Cadence Design Systems , Inc. Sunnyvale, CA. Alta Group. 1994. Fixed-Point Optimizer User's Guide. Cadence Design Systems, Inc. Sunnyvale, CA."},{"key":"e_1_2_1_4_1","first-page":"3","article-title":"Minimization of fixed-point roundoff noise in extended state-space digital filters","author":"Anspach K. M.","year":"1996","unstructured":"Anspach , K. M. , Bomar , B. W. , Engels , R. C. , and Joseph , R. D. 1996 . Minimization of fixed-point roundoff noise in extended state-space digital filters . IEEE Trans. Circuits Syst. II 43, 3 (Mar.). Anspach, K. M., Bomar, B. W., Engels, R. C., and Joseph, R. D. 1996. Minimization of fixed-point roundoff noise in extended state-space digital filters. IEEE Trans. Circuits Syst. II 43, 3 (Mar.).","journal-title":"IEEE Trans. Circuits Syst."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0005-1098(97)00070-8"},{"key":"e_1_2_1_6_1","first-page":"4","article-title":"Scaled normalized lattice digital filter structures","author":"Chung J.-G.","year":"1995","unstructured":"Chung , J.-G. and Parhi , K. K. 1995 . Scaled normalized lattice digital filter structures . IEEE Trans. Circuits Syst. II 42, 4 (Apr.). Chung, J.-G. and Parhi, K. K. 1995. Scaled normalized lattice digital filter structures. IEEE Trans. Circuits Syst. II 42, 4 (Apr.).","journal-title":"IEEE Trans. Circuits Syst."},{"key":"e_1_2_1_7_1","article-title":"Minimum uncorrelated unit noise in state-space digital filtering","author":"Hwang S. Y.","year":"1977","unstructured":"Hwang , S. Y. 1977 . Minimum uncorrelated unit noise in state-space digital filtering . IEEE Transactions on Accoustics, Speech, and Signal Processing ASSP-25, 273--281. Hwang, S. Y. 1977. Minimum uncorrelated unit noise in state-space digital filtering. IEEE Transactions on Accoustics, Speech, and Signal Processing ASSP-25, 273--281.","journal-title":"IEEE Transactions on Accoustics, Speech, and Signal Processing ASSP-25, 273--281."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1970.tb01763.x"},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Jackson L. B. 1970b. Roundoff-noise analysis for fixed-point digital filters realized in cascade or parallel form. In IEEE Transactions on Audio and Electroacoustics AU-18 2 (June). Jackson L. B. 1970b. Roundoff-noise analysis for fixed-point digital filters realized in cascade or parallel form. In IEEE Transactions on Audio and Electroacoustics AU-18 2 (June).","DOI":"10.1109\/TAU.1970.1162084"},{"key":"e_1_2_1_10_1","first-page":"11","article-title":"A floating-point to fixed-point assembly program translator for the TMS 320C25","author":"Kim S.","year":"1994","unstructured":"Kim , S. and Sung , W. 1994 . A floating-point to fixed-point assembly program translator for the TMS 320C25 . IEEE Trans. Circuits Syst. II 41, 11 (Nov.). Kim, S. and Sung, W. 1994. A floating-point to fixed-point assembly program translator for the TMS 320C25. IEEE Trans. Circuits Syst. II 41, 11 (Nov.).","journal-title":"IEEE Trans. Circuits Syst."},{"key":"e_1_2_1_11_1","first-page":"11","article-title":"Fixed-point optimization utility for C and C&plus;&plus; based digital signal processing programs","author":"Kim S.","year":"1998","unstructured":"Kim , S. and Sung , W. 1998 . Fixed-point optimization utility for C and C&plus;&plus; based digital signal processing programs . IEEE Trans. Circuits Syst. II 45, 11 (Nov.). Kim, S. and Sung, W. 1998. Fixed-point optimization utility for C and C&plus;&plus; based digital signal processing programs. IEEE Trans. Circuits Syst. II 45, 11 (Nov.).","journal-title":"IEEE Trans. Circuits Syst."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.936374"},{"volume-title":"Proceedings of the 2nd SUIF Compiler Workshop.","author":"Kum K.-I.","key":"e_1_2_1_13_1","unstructured":"Kum , K.-I. , Kang , J. , and Sung , W . 1997. A floating-point to fixed-point C converter for fixed-point digital signal processors . In Proceedings of the 2nd SUIF Compiler Workshop. Kum, K.-I., Kang, J., and Sung, W. 1997. A floating-point to fixed-point C converter for fixed-point digital signal processors. In Proceedings of the 2nd SUIF Compiler Workshop."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1999.758363"},{"key":"e_1_2_1_15_1","first-page":"9","article-title":"AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors","author":"Kum K.-I.","year":"2000","unstructured":"Kum , K.-I. , Kang , J. , and Sung , W. 2000 . AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors . IEEE Trans. Circuits Syst. II 47, 9 (Sept.), 840--848. Kum, K.-I., Kang, J., and Sung, W. 2000. AUTOSCALER for C: An optimizing floating-point to integer C program converter for fixed-point digital signal processors. IEEE Trans. Circuits Syst. II 47, 9 (Sept.), 840--848.","journal-title":"IEEE Trans. Circuits Syst."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/581630.581674"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1976.1084254"},{"key":"e_1_2_1_18_1","article-title":"Realization of digital filters using block-floating-point arithmetic","volume":"2","author":"Oppeheim A. V.","year":"1970","unstructured":"Oppeheim , A. V. 1970 . Realization of digital filters using block-floating-point arithmetic . IEEE Transactions on Audio and Electroacoustics AU-18 , 2 ( June ). Oppeheim, A. V. 1970. Realization of digital filters using block-floating-point arithmetic. IEEE Transactions on Audio and Electroacoustics AU-18, 2 (June).","journal-title":"IEEE Transactions on Audio and Electroacoustics AU-18"},{"key":"e_1_2_1_19_1","unstructured":"Peng S. 1999. UTDSP: A VLIW programmable DSP processor in 0.35 &mu;m CMOS. M.S. thesis University of Toronto. http:\/\/www.eecg.utoronto.ca\/~speng. Peng S. 1999. UTDSP: A VLIW programmable DSP processor in 0.35 &mu;m CMOS. M.S. thesis University of Toronto. http:\/\/www.eecg.utoronto.ca\/~speng."},{"volume-title":"Proceedings of the 6th ICSPAT. 860--865","author":"Pujare S.","key":"e_1_2_1_20_1","unstructured":"Pujare , S. , Lee , C. G. , and Chow , P . 1995. Machine-independent compiler optimizations for the UofT DSP architecture . In Proceedings of the 6th ICSPAT. 860--865 . Pujare, S., Lee, C. G., and Chow, P. 1995. Machine-independent compiler optimizations for the UofT DSP architecture. In Proceedings of the 6th ICSPAT. 860--865."},{"volume-title":"Proceedings of the ICASSP. II--437--II--440","author":"Saghir M. A.","key":"e_1_2_1_23_1","unstructured":"Saghir , M. A. , Chow , P. , and Lee , C. G . 1994. Application-driven design of DSP architectures and compilers . In Proceedings of the ICASSP. II--437--II--440 . Saghir, M. A., Chow, P., and Lee, C. G. 1994. Application-driven design of DSP architectures and compilers. In Proceedings of the ICASSP. II--437--II--440."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1962.1088681"},{"volume-title":"Proceedings of the 29th IEEE\/ACM International Symposium on Microarchitecture. 262--273","author":"Stoodley M. G.","key":"e_1_2_1_26_1","unstructured":"Stoodley , M. G. and Lee , C. G . 1996. Software pipelining loops with conditional branches . In Proceedings of the 29th IEEE\/ACM International Symposium on Microarchitecture. 262--273 . Stoodley, M. G. and Lee, C. G. 1996. Software pipelining loops with conditional branches. In Proceedings of the 29th IEEE\/ACM International Symposium on Microarchitecture. 262--273."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"volume-title":"Press Release: Synopsys Accelerates System-Level C-Based DSP Design With CoCentric Fixed-Point Designer Tool","author":"Synopsys","key":"e_1_2_1_28_1","unstructured":"Synopsys 2000a. Press Release: Synopsys Accelerates System-Level C-Based DSP Design With CoCentric Fixed-Point Designer Tool . Synopsys Inc . Synopsys 2000a. Press Release: Synopsys Accelerates System-Level C-Based DSP Design With CoCentric Fixed-Point Designer Tool. Synopsys Inc."},{"volume-title":"Synopsys CoCentric Fixed-Point Designer Datasheet","author":"Synopsys","key":"e_1_2_1_29_1","unstructured":"Synopsys 2000b. Synopsys CoCentric Fixed-Point Designer Datasheet . Synopsys Inc . Synopsys 2000b. Synopsys CoCentric Fixed-Point Designer Datasheet. Synopsys Inc."},{"key":"e_1_2_1_30_1","unstructured":"Texas Instruments. 1993. TMS320C5x User's Guide. Texas Instruments. 1993. TMS320C5x User's Guide."},{"volume-title":"Proceedings of the ICASSP.","author":"Willems M.","key":"e_1_2_1_31_1","unstructured":"Willems , M. , Bursgens , V. , Grotker , T. , and Meyr , H . 1997. FRIDGE: An interactive code generation environment for HW\/SW CoDesign . In Proceedings of the ICASSP. Willems, M., Bursgens, V., Grotker, T., and Meyr, H. 1997. FRIDGE: An interactive code generation environment for HW\/SW CoDesign. In Proceedings of the ICASSP."},{"key":"e_1_2_1_32_1","doi-asserted-by":"crossref","unstructured":"Zilles C. and Sohi G. 2002. Master\/slave speculative parallelization. In MICRO-35. 85--96. Zilles C. and Sohi G. 2002. Master\/slave speculative parallelization. In MICRO-35. 85--96.","DOI":"10.1109\/MICRO.2002.1176241"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1347375.1347379","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1347375.1347379","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:38:58Z","timestamp":1750253938000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1347375.1347379"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4]]},"references-count":28,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2008,4]]}},"alternative-id":["10.1145\/1347375.1347379"],"URL":"https:\/\/doi.org\/10.1145\/1347375.1347379","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2008,4]]},"assertion":[{"value":"2004-01-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2007-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-05-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}