{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:35:41Z","timestamp":1750307741670,"version":"3.41.0"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2008,4,1]],"date-time":"2008-04-01T00:00:00Z","timestamp":1207008000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2008,4]]},"abstract":"<jats:p>Most of the work done in the field of code compression pertains to processors with fixed-length instruction encoding. The design of a code-compression scheme for variable-length instruction encodings poses newer design challenges. In this work, we first investigate the scope for code compression on variable-length instruction-set processors whose encodings are already optimized to a certain extent with respect to their usage. For such ISAs instruction boundaries are not known prior to decoding. Another challenging task of designing a code-compression scheme for such ISAs is designing the decompression hardware, which must decompress code postcache so that we gain in performance. We present two dictionary-based code compression schemes. The first algorithm uses a bit-vector; the second one uses reserved instructions to identify code words. We design additional logic for each of the schemes to decompress the code on-the-fly. We test the two algorithms with a variable-length RISC processor. We provide a detailed experimental analysis of the empirical results obtained by extensive simulation-based design space exploration for this system. The optimized decompressor can now execute compressed program faster than the native program. The experiments demonstrate reduction in code size (up to 30%), speed-up (up to 15%), and bus-switching activity (up to 20%). We also implement one decompressor in a hardware description language and synthesize it to illustrate the small overheads associated with the proposed approach.<\/jats:p>","DOI":"10.1145\/1347375.1347388","type":"journal-article","created":{"date-parts":[[2008,5,15]],"date-time":"2008-05-15T18:28:05Z","timestamp":1210876085000},"page":"1-36","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Code compression for performance enhancement of variable-length embedded processors"],"prefix":"10.1145","volume":"7","author":[{"given":"Rajeev","family":"Kumar","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Kharagpur, WB, India"}]},{"given":"Dipankar","family":"Das","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, WB, India"}]}],"member":"320","published-online":{"date-parts":[[2008,5,8]]},"reference":[{"volume-title":"Proceedings of 31st Annual ACM\/IEEE International Symposium on Microarchitecture (Micro). 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In Proceedings of the 30th ACM\/IEEE International Symposium on Microarchitecture (Micro), IEEE Computer Society Press , Los Alamitos, CA. 194--203. Lefurgy, C. R., Bird, P. L., Chen, I. C., and Mudge, T. N. 1997. Improving code density using compression techniques. In Proceedings of the 30th ACM\/IEEE International Symposium on Microarchitecture (Micro), IEEE Computer Society Press, Los Alamitos, CA. 194--203."},{"volume-title":"Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA). IEEE Computer Society Press","author":"Lefurgy C. R.","key":"e_1_2_1_21_1","unstructured":"Lefurgy , C. R. , Piccininni , E. , and Mudge , T. N . 2000. Reducing code size with run-time decompression . In Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA). IEEE Computer Society Press , Los Alamitos, CA. 218--228. Lefurgy, C. R., Piccininni, E., and Mudge, T. N. 2000. Reducing code size with run-time decompression. In Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA). IEEE Computer Society Press, Los Alamitos, CA. 218--228."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277185"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.811316"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337423"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2005.36"},{"volume-title":"Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'). IEEE Computer Society Press","author":"Liao S.","key":"e_1_2_1_26_1","unstructured":"Liao , S. , Devadas , S. , and Keutzer , K . 1995. Code density optimization for embedded DSP processors using data compression techniques . In Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'). IEEE Computer Society Press , Los Alamitos, CA. 272--278. Liao, S., Devadas, S., and Keutzer, K. 1995. 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