{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,11]],"date-time":"2026-04-11T08:44:06Z","timestamp":1775897046205,"version":"3.50.1"},"reference-count":91,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2008,4,1]],"date-time":"2008-04-01T00:00:00Z","timestamp":1207008000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2008,4]]},"abstract":"<jats:p>\n            The determination of upper bounds on execution times, commonly called worst-case execution times (WCETs), is a necessary step in the development and validation process for hard real-time systems. This problem is hard if the underlying processor architecture has components, such as caches, pipelines, branch prediction, and other speculative components. This article describes different approaches to this problem and surveys several commercially available tools\n            <jats:sup>1<\/jats:sup>\n            and research prototypes.\n          <\/jats:p>","DOI":"10.1145\/1347375.1347389","type":"journal-article","created":{"date-parts":[[2008,5,15]],"date-time":"2008-05-15T18:28:05Z","timestamp":1210876085000},"page":"1-53","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1296,"title":["The worst-case execution-time problem\u2014overview of methods and survey of tools"],"prefix":"10.1145","volume":"7","author":[{"given":"Reinhard","family":"Wilhelm","sequence":"first","affiliation":[{"name":"Saarland University, Saarbr\u00fccken, Germany"}]},{"given":"Jakob","family":"Engblom","sequence":"additional","affiliation":[{"name":"Virtutech AB, Stockholm"}]},{"given":"Andreas","family":"Ermedahl","sequence":"additional","affiliation":[{"name":"M\u00e4lardalen University, V\u00e4ster\u00e5s, Sweden"}]},{"given":"Niklas","family":"Holsti","sequence":"additional","affiliation":[{"name":"Tidorum Ltd., Helsinki, Finland"}]},{"given":"Stephan","family":"Thesing","sequence":"additional","affiliation":[{"name":"Saarland University, Saarbr\u00fccken, Germany"}]},{"given":"David","family":"Whalley","sequence":"additional","affiliation":[{"name":"Florida State University, Tallahassee, FL"}]},{"given":"Guillem","family":"Bernat","sequence":"additional","affiliation":[{"name":"Rapita Systems, Ltd."}]},{"given":"Christian","family":"Ferdinand","sequence":"additional","affiliation":[{"name":"AbsInt Angewandte Informatik"}]},{"given":"Reinhold","family":"Heckmann","sequence":"additional","affiliation":[{"name":"AbsInt Angewandte Informatik"}]},{"given":"Tulika","family":"Mitra","sequence":"additional","affiliation":[{"name":"National University of Singapore"}]},{"given":"Frank","family":"Mueller","sequence":"additional","affiliation":[{"name":"North Carolina State University"}]},{"given":"Isabelle","family":"Puaut","sequence":"additional","affiliation":[{"name":"IRISA"}]},{"given":"Peter","family":"Puschner","sequence":"additional","affiliation":[{"name":"Tu Vienna"}]},{"given":"Jan","family":"Staschulat","sequence":"additional","affiliation":[{"name":"TU Braunschweig"}]},{"given":"Per","family":"Stenstr\u00f6m","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology"}]}],"member":"320","published-online":{"date-parts":[[2008,5,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859659"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.2004.19"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the IEEE Real-Time Systems Symposium. Puerto Rico. 172--181","author":"Arnold R.","unstructured":"Arnold , R. , Mueller , F. , Whalley , D. , and Harmon , M . 1994. Bounding worst-case instruction cache performance . In Proceedings of the IEEE Real-Time Systems Symposium. Puerto Rico. 172--181 . Arnold, R., Mueller, F., Whalley, D., and Harmon, M. 1994. Bounding worst-case instruction cache performance. In Proceedings of the IEEE Real-Time Systems Symposium. Puerto Rico. 172--181."},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the 10th European Workshop on Dependable Computing. Austrian Computer Society (OCG). 109--114","author":"Atanassov P.","unstructured":"Atanassov , P. , Haberl , S. , and Puschner , P . 1999. Heuristic worst-case execution time analysis . In Proceedings of the 10th European Workshop on Dependable Computing. Austrian Computer Society (OCG). 109--114 . Atanassov, P., Haberl, S., and Puschner, P. 1999. Heuristic worst-case execution time analysis. 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WCET analysis of probabilistic hard real--time systems. In Proceedings of the 23rd Real-Time Systems Symposium RTSS 2002. Austin, Texas. 279--288."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1233760.1233763"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2005.7"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the 2nd International Workshop on Real-Time Tools (RT-TOOLS'2002)","author":"Carlsson M.","unstructured":"Carlsson , M. , Engblom , J. , Ermedahl , A. , Lindblad , J. , and Lisper , B . 2002. Worst-case execution time analysis of disable interrupt regions in a commercial real-time operating system . In Proceedings of the 2nd International Workshop on Real-Time Tools (RT-TOOLS'2002) . Carlsson, M., Engblom, J., Ermedahl, A., Lindblad, J., and Lisper, B. 2002. Worst-case execution time analysis of disable interrupt regions in a commercial real-time operating system. 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