{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T16:11:07Z","timestamp":1764173467789,"version":"3.41.0"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2008,4,1]],"date-time":"2008-04-01T00:00:00Z","timestamp":1207008000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2008,4]]},"abstract":"<jats:p>In this paper, we describe the development of the Stanford University Carbon Nanotube FET (CNFET) Compact Model. The CNFET Model is a circuit-compatible, compact model which describes enhancement-mode, CMOS-like CNFETs. It can be used to simulate both functionality and performance of large-scale circuits with hundreds of CNFETs. To produce realistic and relevant results, the model accounts for several practical non-idealities such as scattering in the near-ballistic channel, effects of the source\/drain extension region, and charge-screening for multiple-nanotube CNFETs. The model also includes a full transcapacitance network for more accurate transient and AC results. The Stanford University CNFET Model is implemented in both HSPICE macro language and VerilogA. The VerilogA implementation shows speedups of roughly 7x\u223c15x over HSPICE. Applications of the model suggest that n- and p-CNFETs will have 6x and 13x speed advantage over Si n- and p-MOSFETs respectively at the 32nm node, and that a CNT density of 250 CNTs\/um is ideal for multiple-nanotube gates. Such a compact CNFET model will be absolutely essential in ushering in the Design Era of CNFET circuits as carbon nanotube technology outgrows its \u201cscience discovery\u201d phase.<\/jats:p>","DOI":"10.1145\/1350763.1350767","type":"journal-article","created":{"date-parts":[[2008,4,29]],"date-time":"2008-04-29T13:01:12Z","timestamp":1209474072000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Carbon nanotube transistor compact model for circuit design and performance optimization"],"prefix":"10.1145","volume":"4","author":[{"given":"Jie","family":"Deng","sequence":"first","affiliation":[{"name":"Stanford University, Stanford, CA"}]},{"given":"Albert","family":"Lin","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}]},{"given":"Gordon C.","family":"Wan","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}]},{"given":"H.-S. Philip","family":"Wong","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}]}],"member":"320","published-online":{"date-parts":[[2008,4,23]]},"reference":[{"volume-title":"Proceedings of the IEEE International Electron Devices Meeting. 559--562","author":"Amlani I.","key":"e_1_2_1_1_1","unstructured":"Amlani , I. , Lewis , J. , Lee , K. , Zhang , R. , Deng , J. , and Wong , H . -S. P. 2006. First demonstration of AC gain from a single-walled carbon nanotube common-source amplifier . Proceedings of the IEEE International Electron Devices Meeting. 559--562 . Amlani, I., Lewis, J., Lee, K., Zhang, R., Deng, J., and Wong, H.-S. P. 2006. First demonstration of AC gain from a single-walled carbon nanotube common-source amplifier. Proceedings of the IEEE International Electron Devices Meeting. 559--562."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283783"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1888054"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.909030"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.909043"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.902047"},{"volume-title":"Proceedings of the International Solid State Circuits Conference, 70--71","author":"Deng J.","key":"e_1_2_1_7_1","unstructured":"Deng , J. , Patil , N. , Ryu , K. , Badmaev , A. , Zhou , C. , Mitra , S. , and Wong , H . -S. P. 2007d. Carbon nanotube transistor circuits: circuit-level performance benchmarking and design options for living with imperfections . Proceedings of the International Solid State Circuits Conference, 70--71 . Deng, J., Patil, N., Ryu, K., Badmaev, A., Zhou, C., Mitra, S., and Wong, H.-S. P. 2007d. Carbon nanotube transistor circuits: circuit-level performance benchmarking and design options for living with imperfections. Proceedings of the International Solid State Circuits Conference, 70--71."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2007.905039"},{"volume-title":"Proceedings of the 4thIEEE Conference on Nanotechnology, 386--388","author":"Dwyer C.","key":"e_1_2_1_9_1","unstructured":"Dwyer , C. , Cheung , M. , and Sorin , D. J . 2004. Semi-empirical SPICE models for carbon nanotube FET logic . In Proceedings of the 4thIEEE Conference on Nanotechnology, 386--388 . Dwyer, C., Cheung, M., and Sorin, D. J. 2004. Semi-empirical SPICE models for carbon nanotube FET logic. In Proceedings of the 4thIEEE Conference on Nanotechnology, 386--388."},{"volume-title":"Biomedical Engineering Society (BMES) Annual Fall Meeting.","author":"Friesz A. K.","key":"e_1_2_1_10_1","unstructured":"Friesz , A. K. , Parker , A. C. , Zhou , C. W. , Ryu , K. M. , Sanders , J. M. , Deng , J. , and Wong H . -S. P. 2007. A biomimetic carbon nanotube synapse circuit . Biomedical Engineering Society (BMES) Annual Fall Meeting. Friesz, A. K., Parker, A. C., Zhou, C. W., Ryu, K. M., Sanders, J. M., Deng, J., and Wong H.-S. P. 2007. A biomimetic carbon nanotube synapse circuit. Biomedical Engineering Society (BMES) Annual Fall Meeting."},{"volume-title":"Proceedings of the International Electron Devices Meeting, 703--706","author":"Guo J.","key":"e_1_2_1_11_1","unstructured":"Guo , J. , Javey A. , Dai , H. , and Lundstrom , M . 2004. Performance analysis and design optimization of near ballistic carbon nanotube field effect transis . In Proceedings of the International Electron Devices Meeting, 703--706 . Guo, J., Javey A., Dai, H., and Lundstrom, M. 2004. Performance analysis and design optimization of near ballistic carbon nanotube field effect transis. In Proceedings of the International Electron Devices Meeting, 703--706."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1474604"},{"key":"e_1_2_1_13_1","unstructured":"ITRS 2006. International Technology Roadmap for Semiconductors http:\/\/public.itrs.net.  ITRS 2006. International Technology Roadmap for Semiconductors http:\/\/public.itrs.net."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1016\/0022-3697(60)90035-4"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1735965"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl034700o"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1840096"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.835135"},{"key":"e_1_2_1_19_1","doi-asserted-by":"crossref","unstructured":"Skotnicki T. Hutchby J. A. King T.-J. Wong H.-S. P. and Beouff F. 2005. The road to the end of CMOS scaling. IEEE Circuits and Devices Magazine 16--26.  Skotnicki T. Hutchby J. A. King T.-J. Wong H.-S. P. and Beouff F. 2005. The road to the end of CMOS scaling. IEEE Circuits and Devices Magazine 16--26.","DOI":"10.1109\/MCD.2005.1388765"},{"key":"e_1_2_1_20_1","unstructured":"Stanford 2007. Stanford Nano Website http:\/\/nano.stanford.edu.  Stanford 2007. Stanford Nano Website http:\/\/nano.stanford.edu."},{"key":"e_1_2_1_21_1","unstructured":"Wan G. C. 2007. Circuit compatible CNFET device model in VerilogA (Talk). (unpublished results).  Wan G. C. 2007. Circuit compatible CNFET device model in VerilogA (Talk). (unpublished results)."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.462.0133"},{"volume-title":"Proceedings of the International Solid State Circuits Conference. 370--371","author":"Wong H.-S. P.","key":"e_1_2_1_23_1","unstructured":"Wong , H.-S. P. , Appenzeller , J. , Derycke , V. , Martel , R. , Wind , S. , and Avouris , P . 2003. Carbon nanotube field effect transistors -- fabrication, device physics, and circuit implications . In Proceedings of the International Solid State Circuits Conference. 370--371 . Wong, H.-S. P., Appenzeller, J., Derycke, V., Martel, R., Wind, S., and Avouris, P. 2003. Carbon nanotube field effect transistors -- fabrication, device physics, and circuit implications. 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