{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:38Z","timestamp":1750307798055,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,4,5]],"date-time":"2008-04-05T00:00:00Z","timestamp":1207353600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,4,5]]},"DOI":"10.1145\/1353610.1353622","type":"proceedings-article","created":{"date-parts":[[2008,4,8]],"date-time":"2008-04-08T16:27:59Z","timestamp":1207672079000},"page":"59-64","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Circuit and physical design of the MDGRAPE-4 on-chip network links"],"prefix":"10.1145","author":[{"given":"Duraid","family":"Madina","sequence":"first","affiliation":[{"name":"Tokyo University, Meguro, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Makoto","family":"Taiji","sequence":"additional","affiliation":[{"name":"RIKEN, Tsurumi, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,4,5]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Raphael NXT is a product of Synopsys Inc. See http:\/\/www.synopsys.com for details.  Raphael NXT is a product of Synopsys Inc. See http:\/\/www.synopsys.com for details."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278582"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234386"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1167704.1167712"},{"key":"e_1_3_2_1_5_1","first-page":"364","volume-title":"VMIC Conference","author":"Coz Y. L. L.","year":"1991","unstructured":"Y. L. L. Coz and R. B. Iverson . A high-speed capacitance extraction algorithm for multi-level vlsi interconnects . In VMIC Conference , pages 364 -- 365 , 1991 . Y. L. L. Coz and R. B. Iverson. A high-speed capacitance extraction algorithm for multi-level vlsi interconnects. In VMIC Conference, pages 364--365, 1991."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320869"},{"key":"e_1_3_2_1_7_1","first-page":"49","volume-title":"IEEE Symposium on VLSI Technology Digest of Technical Papers","author":"K.","year":"2003","unstructured":"K. G. et al. High performance 35nm gate cmosfets with vertical scaling and total stress control for 65nm technology . In IEEE Symposium on VLSI Technology Digest of Technical Papers , pages 49 -- 50 , 2003 . K. G. et al. High performance 35nm gate cmosfets with vertical scaling and total stress control for 65nm technology. In IEEE Symposium on VLSI Technology Digest of Technical Papers, pages 49--50, 2003."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373469"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234260"},{"key":"e_1_3_2_1_10_1","author":"Kuboki T.","year":"2007","unstructured":"T. Kuboki , A. Tsuchiya , and H. Onodera . Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver. IEICE Trans Electron, E90-C(6):1274--1281 , 2007 . T. Kuboki, A. Tsuchiya, and H. Onodera. Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver. IEICE Trans Electron, E90-C(6):1274--1281, 2007.","journal-title":"IEICE Trans Electron, E90-C(6):1274--1281"},{"key":"e_1_3_2_1_11_1","volume-title":"The MDGRAPE-4 Supercomputer. (forthcoming)","author":"Madina D.","year":"2008","unstructured":"D. Madina . The MDGRAPE-4 Supercomputer. (forthcoming) , Tokyo University , 2008 . D. Madina. The MDGRAPE-4 Supercomputer. (forthcoming), Tokyo University, 2008."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373470"},{"key":"e_1_3_2_1_13_1","volume-title":"Hot Chips Conference","author":"Taiji M.","year":"2003","unstructured":"M. Taiji . Mdgrape-3 chip : A 165-gflops application-specific lsi for molecular dynamics simulations . In Hot Chips Conference , 2003 . M. Taiji. Mdgrape-3 chip: A 165-gflops application-specific lsi for molecular dynamics simulations. In Hot Chips Conference, 2003."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10107-004-0559-y"}],"event":{"name":"SLIP08: International Workshop on System Level Interconnect Prediction","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Newcastle United Kingdom","acronym":"SLIP08"},"container-title":["Proceedings of the 2008 international workshop on System level interconnect prediction"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1353610.1353622","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1353610.1353622","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:28Z","timestamp":1750254988000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1353610.1353622"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4,5]]},"references-count":14,"alternative-id":["10.1145\/1353610.1353622","10.1145\/1353610"],"URL":"https:\/\/doi.org\/10.1145\/1353610.1353622","relation":{},"subject":[],"published":{"date-parts":[[2008,4,5]]},"assertion":[{"value":"2008-04-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}