{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:36:38Z","timestamp":1750307798452,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,4,5]],"date-time":"2008-04-05T00:00:00Z","timestamp":1207353600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,4,5]]},"DOI":"10.1145\/1353610.1353624","type":"proceedings-article","created":{"date-parts":[[2008,4,8]],"date-time":"2008-04-08T16:27:59Z","timestamp":1207672079000},"page":"65-72","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk"],"prefix":"10.1145","author":[{"given":"Basel","family":"Halak","sequence":"first","affiliation":[{"name":"Newcastle University, Newcastle upon Tyne, United Kngdm"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Santosh","family":"Shedabale","sequence":"additional","affiliation":[{"name":"Newcastle University, Newcastle upon Tyne, United Kngdm"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiran","family":"Ramakrishnan","sequence":"additional","affiliation":[{"name":"Newcastle University, Newcastle upon Tyne, United Kngdm"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex","family":"Yakovlev","sequence":"additional","affiliation":[{"name":"Newcastle University, Newcastle upon Tyne, United Kngdm"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gordon","family":"Russell","sequence":"additional","affiliation":[{"name":"Newcastle University, Newcastle upon Tyne, United Kngdm"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2008,4,5]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"High performance CMOS variability in the 65-nm regime and beyond,\" IBM &amp","author":"Bernstin K.","year":"2006","unstructured":"K. Bernstin , \" High performance CMOS variability in the 65-nm regime and beyond,\" IBM &amp ; DEV.VOL. 50. NO. 4\/5 July\/September, 2006 . K. Bernstin et al., \"High performance CMOS variability in the 65-nm regime and beyond,\" IBM & DEV.VOL. 50. NO. 4\/5 July\/September, 2006."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.88"},{"key":"e_1_3_2_1_3_1","unstructured":"Sani R. Nassif \"Modeling and analysis of manufacturing variations \" Proceedings of Custom Integrated Circuits 2001.  Sani R. Nassif \"Modeling and analysis of manufacturing variations \" Proceedings of Custom Integrated Circuits 2001."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"e_1_3_2_1_5_1","volume-title":"DFM\/DFY design for manufacturability and yield -- influence of process variations in digital, analog and mixed-signal circuit design,\" Proceedings of DATE 2006 special session","author":"Buhler M.","year":"2006","unstructured":"M. Buhler , \" DFM\/DFY design for manufacturability and yield -- influence of process variations in digital, analog and mixed-signal circuit design,\" Proceedings of DATE 2006 special session , 2006 . M. Buhler et al., \"DFM\/DFY design for manufacturability and yield -- influence of process variations in digital, analog and mixed-signal circuit design,\" Proceedings of DATE 2006 special session, 2006."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/66.286858"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/66.843636"},{"key":"e_1_3_2_1_8_1","volume-title":"Newcastle University","author":"Shedabale S.","year":"2007","unstructured":"S. Shedabale , S. Chattopadhyay , H. Ramakrishnan , S. Uppal , A. Yakovlev , and A. G. O'Neill , \"Statistical Analysis and Variability Modelling for 0. 3-\u03bcm n-MOS Si Process,\" Post Graduate Conference , Newcastle University , 2007 . S. Shedabale, S. Chattopadhyay, H. Ramakrishnan, S. Uppal, A. Yakovlev, and A. G. O'Neill, \"Statistical Analysis and Variability Modelling for 0.3-\u03bcm n-MOS Si Process,\" Post Graduate Conference, Newcastle University, 2007."},{"key":"e_1_3_2_1_9_1","first-page":"12","volume-title":"Area and energy-efficient crosstalk avoidance codes for on-chip buses\" Proceedings of IEEE International Conference on VLSI in Computers and Processors","author":"Sridhara S. R.","year":"2004","unstructured":"S. R. Sridhara , A. Ahmed and N. R. Shanbhag , \" Area and energy-efficient crosstalk avoidance codes for on-chip buses\" Proceedings of IEEE International Conference on VLSI in Computers and Processors , 2004 , Page(s): 12 -- 17 . S. R. Sridhara, A. Ahmed and N. R. Shanbhag, \"Area and energy-efficient crosstalk avoidance codes for on-chip buses\" Proceedings of IEEE International Conference on VLSI in Computers and Processors, 2004, Page(s):12 -- 17."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.76"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996806"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"IEEE Transactions on Circuits and Systems 2006 53 12 Bit-Error-Rate Estimation for High-Speed Serial Links","DOI":"10.1109\/TCSI.2006.883852"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810800"},{"key":"e_1_3_2_1_14_1","first-page":"343","volume-title":"Wong et al. Nano-CMOS circuits and physical design","author":"P.","year":"2005","unstructured":"Ban P. Wong et al. Nano-CMOS circuits and physical design . Wiley and Sons, Inc. , Hoboken, New Jersy, 2005 , pp. 343 -- 385 . Ban P. Wong et al. Nano-CMOS circuits and physical design. Wiley and Sons, Inc., Hoboken, New Jersy, 2005, pp. 343--385."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337365"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1231996.1232006"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855954"},{"key":"e_1_3_2_1_18_1","volume-title":"Design and Analysis of Experiments","author":"Montgomery D.C.","year":"2001","unstructured":"D.C. Montgomery , Design and Analysis of Experiments , 5 th edition: John Wiley & amp; Sons, INC., 2001 . D.C. Montgomery, Design and Analysis of Experiments, 5th edition: John Wiley & Sons, INC., 2001.","edition":"5"},{"key":"e_1_3_2_1_19_1","unstructured":"International Technology Roadmap for Semiconductors (www.itrs.net).  International Technology Roadmap for Semiconductors (www.itrs.net)."}],"event":{"name":"SLIP08: International Workshop on System Level Interconnect Prediction","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Newcastle United Kingdom","acronym":"SLIP08"},"container-title":["Proceedings of the 2008 international workshop on System level interconnect prediction"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1353610.1353624","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1353610.1353624","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:56:28Z","timestamp":1750254988000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1353610.1353624"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4,5]]},"references-count":19,"alternative-id":["10.1145\/1353610.1353624","10.1145\/1353610"],"URL":"https:\/\/doi.org\/10.1145\/1353610.1353624","relation":{},"subject":[],"published":{"date-parts":[[2008,4,5]]},"assertion":[{"value":"2008-04-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}