{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:35:47Z","timestamp":1750307747920,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2008,4,6]],"date-time":"2008-04-06T00:00:00Z","timestamp":1207440000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2008,4,6]]},"DOI":"10.1145\/1356058.1356073","type":"proceedings-article","created":{"date-parts":[[2008,4,8]],"date-time":"2008-04-08T16:27:59Z","timestamp":1207672079000},"page":"104-113","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Latency-tolerant software pipelining in a production compiler"],"prefix":"10.1145","author":[{"given":"Sebastian","family":"Winkel","sequence":"first","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, USA"}]},{"given":"Rakesh","family":"Krishnaiyer","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, USA"}]},{"given":"Robyn","family":"Sampson","sequence":"additional","affiliation":[{"name":"Intel Corporation, Nashua, NH, USA"}]}],"member":"320","published-online":{"date-parts":[[2008,4,6]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/255235.255275"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3337-2_4"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/106972.106979"},{"volume-title":"Proceedings of the First IEEE\/ACM International Symposium on Code Generation and Optimization (CGO)","year":"2003","author":"Collard J.-F.","key":"e_1_3_2_1_4_1"},{"journal-title":"An Overview of the Intel R IA-64 Compiler. Intel Technology Journal, (Q4)","year":"1999","author":"Dulong C.","key":"e_1_3_2_1_5_1"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1765931.1765961"},{"key":"e_1_3_2_1_8_1","unstructured":"Intel. Intel Itanium 2 Processor Reference Manual for Software Development and Optimization May 2004.  Intel. Intel Itanium 2 Processor Reference Manual for Software Development and Optimization May 2004."},{"key":"e_1_3_2_1_9_1","unstructured":"Intel. Dual--Core Update to the Intel Itanium 2 Processor Reference Manual for Software Development and Optimization Jan. 2006.  Intel. Dual--Core Update to the Intel Itanium 2 Processor Reference Manual for Software Development and Optimization Jan. 2006."},{"key":"e_1_3_2_1_10_1","unstructured":"Intel. Intel Itanium Architecture Software Developer's Manuals Volumes 1-3 Jan. 2006.  Intel. Intel Itanium Architecture Software Developer's Manuals Volumes 1-3 Jan. 2006."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155117"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54022"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/243846.243879"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/846216.846986"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/143365.143488"},{"volume-title":"Proceedings of the First Workshop on EPIC Architectures and Compiler Technology (EPIC-1)","year":"2001","author":"Muthukumar K.","key":"e_1_3_2_1_16_1"},{"volume-title":"Wong. Static Identification of Delinquent Loads. In Proceedings of the Second Annual IEEE\/ACM International Symposium on Code Generation and Optimization (CGO)","year":"2004","author":"Panait V.-M.","key":"e_1_3_2_1_17_1"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/143095.143141"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266833"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.248"}],"event":{"name":"CGO '08: 6th Annual IEEE \/ ACM International Symposium on Code Generation and Optimization","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","ACM Association for Computing Machinery","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Boston MA USA","acronym":"CGO '08"},"container-title":["Proceedings of the 6th annual IEEE\/ACM international symposium on Code generation and optimization"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1356058.1356073","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1356058.1356073","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T13:39:09Z","timestamp":1750253949000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1356058.1356073"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4,6]]},"references-count":20,"alternative-id":["10.1145\/1356058.1356073","10.1145\/1356058"],"URL":"https:\/\/doi.org\/10.1145\/1356058.1356073","relation":{},"subject":[],"published":{"date-parts":[[2008,4,6]]},"assertion":[{"value":"2008-04-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}